Ethernet Master Clock Synchronization After Sleep

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Solution Overview

Problem

In Gigabit Ethernet systems using asymmetric mechanisms, the master device cannot synchronize with the slave device after waking up from a long sleep in quiet mode, leading to data reception errors due to clock drift, as the slave device cannot perform timing recovery without receiving a free running clock from the master device.

Innovation Solution

A master device with a receiver, buffer, phase lock loop unit, and transmitter that generates phase adjustment data from transmission data sent by the slave device, accumulates this data to output a phase adjustment value, and adjusts the output clock to maintain a fixed phase difference with the recovery clock, ensuring synchronization upon waking up and preventing data corruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the master device enters quiet mode to save power, then power consumption is reduced, but clock synchronization is lost after waking up

Engineering Contradiction:

Improvepower consumptionVSAvoidclock synchronization

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The slave device continuously transmits data during quiet mode to maintain the master device's timing recovery capability. This preliminary action ensures that when the master device wakes up, it already has synchronized clock information, eliminating the need for re-synchronization and preventing data reception errors.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The slave device acts as an intermediary by continuously transmitting data signals that carry timing information. These signals serve as a mediator that maintains the master device's clock synchronization even when the master is in quiet mode, allowing the master to resume synchronized operation immediately upon waking.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Use of energy by moving object

If the slave device cannot perform timing recovery without receiving free running clock, then power saving is achieved, but data reception errors occur after master wakes up

Engineering Contradiction:

Improvepower consumptionVSAvoidtiming recovery accuracy

Core Design Contradiction:

Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The slave device maintains continuous data transmission during quiet mode to ensure uninterrupted timing information flow to the master device. This continuous useful action keeps the master's timing recovery operational throughout the quiet period, ensuring seamless transition back to normal operation without synchronization loss.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If idle sequences are continuously sent for synchronization, then clock synchronization is maintained, but power consumption increases

Engineering Contradiction:

Improveclock synchronizationVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the essential synchronization function from the traditional idle sequence mechanism. Instead of sending dedicated idle sequences for synchronization, the system utilizes the existing data transmission from the slave device as the synchronization carrier, eliminating redundant synchronization signals and reducing power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The data transmission from the slave device serves multiple functions simultaneously: it carries actual data information and also provides continuous timing recovery information for the master device. This multi-functionality eliminates the need for separate synchronization signals, achieving both data transmission and clock synchronization with a single signal stream.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution allows the master device to adjust its clock phase to match the slave device's clock phase upon waking, preventing data reception errors and maintaining synchronization, thereby reducing power consumption and data corruption.

Implementation Method 1

a phase lock loop unit for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock

Methodology Applied

Scientific EffectPhase lock loop:

Data Source

PatentUS8284794B2Ethernet system and related clock synchronization method

Publication Date: 2012.10.09 REALTEK SEMICON CORP

AI summary

A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.