Ethernet OTN Synchronization via Timing Markers

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Solution Overview

Problem

Current Ethernet and Optical Transport Network (OTN) technologies are asynchronous and unable to carry true clocks, such as stratum clocks, leading to challenges in network synchronization and reliability, especially when transitioning away from SONET/SDH systems.

Innovation Solution

Incorporating timing markers or symbols into Ethernet and OTN packets to enable downstream devices to recover timing based on time differentials, allowing for the transportation of synchronization signals over asynchronous Ethernet and OTN streams, and enabling frame decomposition for deterministic bandwidth allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If Ethernet and OTN are used as transport technology, then network evolution to unified Ethernet network is enabled and cost is reduced, but ability to carry true clock signals is lost and synchronization reliability deteriorates

Engineering Contradiction:
Improvenetwork evolution capabilityVSAvoidsynchronization reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces timing markers as intermediary elements that mediate between asynchronous Ethernet/OTN transport and synchronous timing requirements. These markers are inserted into the data stream at known intervals and positions, enabling receiving devices to recover clock signals without requiring the transport medium itself to be synchronous. This resolves the contradiction by allowing Ethernet/OTN to carry timing information while maintaining their asynchronous, cost-effective nature.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter of timing delivery from direct clock signal transmission (requiring synchronous transport) to indirect timing marker insertion (compatible with asynchronous transport). By embedding timing markers at specific intervals within the Ethernet or OTN frame structure, the system enables clock recovery in asynchronous environments, thus maintaining synchronization reliability while using cost-effective Ethernet/OTN infrastructure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If timing markers are inserted into Ethernet/OTN packets, then clock recovery capability is enabled, but packet structure complexity increases

Engineering Contradiction:
Improveclock recovery capabilityVSAvoidpacket structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The timing markers are designed to serve multiple functions simultaneously: they provide clock recovery information, enable synchronization, and can be integrated with existing Ethernet/OTN frame structures. By making the timing marker system multi-functional and compatible with standard protocols, the patent minimizes additional complexity while maximizing timing recovery capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies timing markers at specific local positions within the packet structure (such as in overhead fields or at defined intervals in the payload) rather than requiring changes to the entire packet structure. This localized approach allows clock recovery functionality to be added without fundamentally altering the overall packet format, thus limiting the increase in structural complexity.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If adaptive clock recovery over pseudowire emulation is used, then soft clock distribution is enabled, but clock quality and reliability deteriorate due to jitter buffer issues

Engineering Contradiction:
Improveadaptive clock distribution capabilityVSAvoidclock quality
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Instead of adapting the clock based on receiver conditions (reactive approach), the patent inserts timing markers at predetermined positions and intervals in the transmitted stream (proactive approach). This preliminary structuring of timing information allows the receiving end to directly recover the clock without needing to adjust jitter buffers or adapt to varying conditions, thereby maintaining higher clock quality and reliability while preserving adaptive distribution capability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9100133B2Methods and systems for carrying synchronization over ethernet and optical transport network
Publication Date: 2015.08.04 CIENA CORP
  • US9100133B2 patent drawing
  • US9100133B2 patent drawing
  • US9100133B2 patent drawing

AI summary

The present disclosure relates to carrying synchronization through Ethernet, Optical Transport Network (OTN), and other asynchronous protocols. In one exemplary embodiment, timing markers or symbols are used in packets to enable a downstream device to recover timing based upon a time differential between markers or symbols. Advantageously, enabling Ethernet, OTN, etc. to carry synchronous information will de-risk switching from SONET/SDH to Ethernet and/or OTN for service providers. The present disclosure also includes frame decomposition scheme of the Ethernet stream. Ethernet packets are broken into fixed bandwidth and excess bandwidth. The fixed bandwidth is subdivided into fixed (negotiated) flits, with each flit corresponding to a specific user or combination of users like a private tunnel. This offers service providers a method to provide deterministic and more secure bandwidth over Ethernet to multiple clients.