Ethernet PHY Integrated PCS and FEC Sub-layers

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Solution Overview

Problem

Ethernet physical layer devices face challenges in reducing latency, costs, and chip area consumption due to the separate architectures of physical coding and forward error correction sub-layers, which require redundant components for compensating processing overheads like code word mark insertion and removal.

Innovation Solution

Integration of physical coding and forward error correction sub-layers with data stream halting blocks that compensate for processing delays caused by code word mark inserters and removers, eliminating the need for redundant components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate architectures of physical coding and forward error correction sub-layers are used, then processing overheads can be compensated with redundant components, but chip area consumption increases

Engineering Contradiction:

Improveprocessing overhead compensationVSAvoidchip area consumption

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the physical coding sub-layer (PCS) and forward error correction sub-layer (FEC) into a single integrated device. The integration block merges previously separate components including the CWM inserter, CWM remover, and data stream halting functionality into one unified structure, eliminating redundant components and reducing chip area while maintaining the ability to compensate for processing overheads.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integration block performs multiple functions within a single component: it manages code word mark insertion, code word mark removal, data stream halting, and coordination between PCS and FEC operations. This multi-functional design replaces what previously required separate dedicated components, reducing overall device complexity and chip area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If separate architectures of physical coding and forward error correction sub-layers are used, then processing overheads can be compensated with redundant components, but device complexity increases

Engineering Contradiction:

Improveprocessing overhead compensationVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the PCS and FEC sub-layers into a single integrated device with a unified integration block. This consolidation reduces device complexity by eliminating the need for separate redundant components while preserving the functional capabilities needed for processing overhead compensation through coordinated operation within the integrated structure.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If separate architectures of physical coding and forward error correction sub-layers are used, then processing overheads can be compensated with redundant components, but latency increases

Engineering Contradiction:

Improveprocessing overhead compensationVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The integration block combines previously separate processing functions into a unified structure, enabling coordinated operation that reduces the number of processing stages and inter-component data transfers. This merging eliminates redundant processing steps while maintaining overhead compensation capabilities, thereby reducing overall latency.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If separate architectures of physical coding and forward error correction sub-layers are used, then processing overheads can be compensated with redundant components, but costs increase

Engineering Contradiction:

Improveprocessing overhead compensationVSAvoidcosts

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent integrates PCS and FEC into a single device structure, reducing the total component count and simplifying manufacturing processes. The integration block consolidates multiple functions that previously required separate components, leading to lower production costs while maintaining the ability to compensate for processing overheads through coordinated internal operation.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10411832B2Ethernet physical layer device having integrated physical coding and forward error correction sub-layers

Publication Date: 2019.09.10 MARVELL ASIA PTE LTD

AI summary

Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.