Ethernet PHY Data Distribution for Flexible Multi-Rate Bandwidth
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Solution Overview
Problem
Current Ethernet interface designs require multiple types of physical subboards and chips due to different bandwidth rates, leading to a heavy workload and increased costs, as existing fixed-rate single-port Ethernet interfaces struggle to meet complex bandwidth configurations and have limited application scenarios.
Innovation Solution
A data distribution method that processes packet streams by dividing them into data blocks, performing physical layer encoding, scrambling, and alignment marker insertion, and then distributing these streams across multiple second circuits in a physical layer circuit, allowing for flexible bandwidth configuration and resource reuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple types of physical subboards and Ethernet interface chips are designed for different bandwidth rates, then different bandwidth configurations can be supported, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a universal physical subboard design where a single type of subboard can support multiple Ethernet interface rates (10GE, 25GE, 40GE, 100GE) through software configuration and dynamic resource allocation. The MAC layer is divided into multiple virtual MACs, each capable of operating at different rates, allowing one physical subboard to replace multiple specialized subboards.
Solution Approach 2:
The MAC layer is segmented into multiple virtual MACs (VMACs), where each VMAC can be independently configured for different Ethernet rates. This segmentation allows the system to present different logical interfaces while using a unified physical hardware platform, reducing the need for multiple physical subboard types.
2Adaptability or versatility
If multiple types of Ethernet interface chips are used for different subboards, then different bandwidth rates can be achieved, but workload and design complexity increase
Solution Approach 1:
The patent employs a universal Ethernet interface chip design that can operate at multiple rates (10GE, 25GE, 40GE, 100GE) through configurable MAC layers. Instead of designing separate chips for each rate, a single chip family is developed that supports all rates via software configuration, significantly reducing design workload and manufacturing complexity.
Solution Approach 2:
The system changes operational parameters (MAC layer configuration, bandwidth allocation) rather than changing hardware parameters (chip type, subboard model). This allows the same physical chip to adapt to different bandwidth requirements through parameter adjustment, eliminating the need for multiple specialized chip designs.
3Device complexity
If fixed-rate single-port Media Access Control protocol layer interfaces are used, then implementation is simplified, but complex bandwidth configuration requirements cannot be met
Solution Approach 1:
The patent transforms the static fixed-rate MAC interface into a dynamic multi-rate interface. The MAC layer can dynamically allocate bandwidth and switch between different rates (10GE, 25GE, 40GE, 100GE) based on traffic requirements. This dynamic capability allows the system to meet complex bandwidth configuration needs while maintaining relatively simple implementation through a unified interface design.
Solution Approach 2:
The MAC layer is segmented into multiple virtual MACs that can be independently configured for different rates and bandwidth allocations. This segmentation enables complex bandwidth configurations to be achieved through logical division rather than requiring multiple separate physical interfaces, simplifying the overall implementation while enhancing adaptability.
Data Source
AI summary
A data distribution method, a data aggregation method, and related apparatuses are disclosed. The data distribution method may include: receiving a first packet stream; dividing the first packet stream to obtain a first data block stream; sending the first data block stream to a first circuit; processing, by the first circuit, the first data block stream to obtain a first data stream; distributing, by the first circuit, the first data stream to N1 second circuits of M second circuits in a PHY, where M is greater than N1, N1 is a positive integer, and M is a positive integer; and processing, by the N1 second circuits, the received first data stream to obtain N1 first code streams. The technical solutions provided by the embodiments of the present invention help to meet a requirement for complex bandwidth configuration and extend an application scenario.