Ethernet PHY Data Distribution for Flexible Multi-Rate Bandwidth
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Solution Overview
Problem
Current Ethernet interface designs require multiple types of physical subboards and chips due to different bandwidth rates, leading to a heavy workload and increased costs, as existing fixed-rate single-port Ethernet interfaces struggle to meet complex bandwidth configuration requirements.
Innovation Solution
A data distribution method that involves receiving a packet stream, dividing it into data blocks, processing, and distributing the data streams to multiple second circuits in a physical layer circuit, allowing for flexible bandwidth configuration and resource reuse by selectively enabling only necessary circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple types of physical subboards and Ethernet interface chips are designed for different bandwidth rates, then different bandwidth rates can be supported, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a universal physical subboard that can operate at multiple bandwidth rates (10G, 25G, 40G, 100G) by using a single type of Ethernet interface chip. The subboard includes multiple circuits that can be selectively activated based on the required bandwidth, eliminating the need for separate specialized subboards for each rate and thereby reducing device complexity while maintaining adaptability.
Solution Approach 2:
The patent introduces dynamic bandwidth configuration capability where the Ethernet interface can adaptively adjust its operating rate based on traffic requirements. The system includes control logic that dynamically selects which circuits to activate and configures the interface accordingly, allowing a single subboard type to serve multiple bandwidth needs without requiring manual reconfiguration or hardware changes.
2Adaptability or versatility
If multiple types of Ethernet interface chips are designed for different subboards, then different bandwidth rates can be supported, but workload and development cost increase
Solution Approach 1:
The patent employs a single type of Ethernet interface chip that is designed to support multiple bandwidth rates through software or configuration-based control rather than requiring separate specialized chips for each rate. This universal chip design significantly reduces the development workload and associated costs while maintaining the ability to support various bandwidth requirements through selective circuit activation.
3Device complexity
If a fixed-rate single-port Ethernet interface is used, then implementation is simple, but complex bandwidth configuration requirements cannot be met
Solution Approach 1:
The patent transforms the static fixed-rate interface into a dynamic multi-rate interface by incorporating control logic that can selectively activate different circuits based on bandwidth requirements. The system dynamically configures the interface rate and port availability in response to traffic demands, maintaining implementation simplicity while achieving complex bandwidth configuration capabilities through automated control rather than manual setup.
4Adaptability or versatility
If all circuits in the physical layer circuit are always enabled, then maximum bandwidth capability is maintained, but energy consumption increases
Solution Approach 1:
The patent implements dynamic circuit activation where only the necessary circuits required for the current bandwidth rate are enabled, while unnecessary circuits are deactivated to save energy. For example, when operating at 10G rate, only the circuits needed for that rate remain active, whereas circuits for higher rates are powered down. This dynamic adaptation maintains full bandwidth capability when needed while significantly reducing energy consumption during lower-rate operation.
Solution Approach 2:
The system selectively deactivates and reactivates circuits based on current bandwidth requirements. When high bandwidth is not needed, certain circuits are discarded (powered down) to reduce energy consumption, and can be quickly recovered (reactivated) when higher bandwidth becomes necessary, optimizing the balance between performance and energy efficiency.
Data Source
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Figure 2-b~2-c
AI summary
A data distribution method, a data aggregation method, and related apparatuses are disclosed. The data distribution method may include: receiving a first packet stream; dividing the first packet stream to obtain a first data block stream; sending the first data block stream to a first circuit; processing, by the first circuit, the first data block stream to obtain a first data stream; distributing, by the first circuit, the first data stream to N1 second circuits of M second circuits in a PHY, where M is greater than N1, N1 is a positive integer, and M is a positive integer; and processing, by the N1 second circuits, the received first data stream to obtain N1 first code streams. The technical solutions provided by the embodiments of the present invention help to meet a requirement for complex bandwidth configuration and extend an application scenario.