Ethernet PHY Timestamping in the MDI Clock Domain for Precise PTP Sync
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Solution Overview
Problem
Existing Ethernet clock synchronization techniques, such as IEEE 1588 (PTP), face inaccuracies in timestamping due to reliance on predetermined offsets for processing delays, which are not precise enough for high-speed Ethernet communications, leading to uncertainties in clock synchronization.
Innovation Solution
Timestamping Ethernet PHY frames by generating timestamps based on the timing of PHY frames exchanged between the physical coding sublayer (PCS) and the physical medium attachment sublayer (PMA) within the same clock domain as the media-dependent interface (MDI), adjusting for processing delays associated with these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If predetermined offsets are used to adjust timestamps for processing delays, then the timestamping process is simple, but the precision of timing information deteriorates
Solution Approach 1:
The patent extracts and measures the actual processing delay between MII and MDI interfaces by capturing timestamps at both ends during packet transmission. Instead of using a predetermined offset, the system measures the real delay experienced by each packet and uses this measured value to adjust the timestamp, thereby achieving high precision timing information.
2Adaptability or versatility
If timestamps are captured in different clock domains, then the timestamping can be performed at different layers, but uncertainties from clock domain crossings increase
Solution Approach 1:
The patent applies equipotentiality by ensuring that timestamp capture and adjustment operations occur within the same clock domain (MDI clock domain). By translating timestamps from MII clock domain to MDI clock domain using measured delay values, the system eliminates clock domain crossing uncertainties and maintains consistent timing reference throughout the process.
3Speed
If high-speed Ethernet communications are supported, then the data rate increases, but the precision requirements for clock synchronization become more stringent
Solution Approach 1:
The patent implements feedback by continuously measuring the actual processing delay between interfaces using packet timestamps and using this measured feedback to adjust subsequent timestamp calculations. This closed-loop approach ensures that even at high Ethernet speeds, the clock synchronization precision is maintained by compensating for variations in processing delay.
Data Source
AI summary
This disclosure provides methods, devices, and systems for timestamping Ethernet packets. The present implementations more specifically relate to capturing timestamps in the same clock domain as a media-dependent interface (MDI). In some aspects, a physical layer (PHY) transceiver may generate a receive (RX) timestamp for a precision time protocol (PTP) packet based on a time at which a physical medium attachment (PMA) sublayer outputs, to a physical coding sublayer (PCS), one or more PHY frames carrying the PTP packet. In some other aspects, a PHY transceiver may generate a transmit (TX) timestamp for a PTP packet based on a time at which a PCS outputs a reference frame to a PMA sublayer, where the reference frame precedes one or more PHY frames carrying the PTP packet.