Ethernet Transmit Buffer Management with Per Priority Pause Flow Control

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Solution Overview

Problem

In Ethernet transmit implementations, the storage requirements become significant with larger packet sizes and multiple traffic classes, leading to head-of-line blocking and buffer explosion issues, especially when Per Priority Pause is enabled, requiring large RAM or FIFO sizes to prevent blocking.

Innovation Solution

The system manages transmit buffering by storing packet descriptors on-chip until packets initiate transmission, flushing paused packets from the RAM or FIFO, and reinstating them when their traffic class is unpaused, allowing packets to be reselected and transmitted in their original order, reducing buffer requirements by storing only active packets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a FIFO stores the entire packet before transmission to prevent underflow, then transmission reliability is improved, but buffer memory size increases significantly with multiple traffic classes

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidbuffer memory size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the buffer into multiple FIFOs, one for each traffic class. Each FIFO stores packets for a specific traffic class, allowing independent management and preventing head-of-line blocking while maintaining transmission reliability for each class separately.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary actions by checking the pause status of traffic classes before fetching packets into the FIFO. The system determines which traffic class to service before the packet is fetched from memory, preventing wasted buffer space on paused traffic classes and reducing overall buffer requirements.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If a single FIFO is shared between different traffic classes, then buffer memory size is reduced, but head-of-line blocking occurs when a paused packet occupies the FIFO

Engineering Contradiction:
Improvebuffer memory sizeVSAvoidtransmission throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides the single shared FIFO into multiple class-specific FIFOs. This segmentation allows packets from different traffic classes to be stored and transmitted independently, eliminating head-of-line blocking where a paused packet would prevent other classes from using the buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic selection of which traffic class to service based on current pause status. The system dynamically determines which FIFO to access next, allowing flexible adaptation to changing network conditions while maintaining efficient buffer utilization.

Inventive Principle:
Principle #15Dynamics

3Productivity

If RAM is used instead of FIFO to fetch packets out of order, then head-of-line blocking is avoided, but buffer memory size increases to store packets from multiple traffic classes

Engineering Contradiction:
Improvetransmission flexibilityVSAvoidbuffer memory size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the RAM-based buffer into multiple class-specific FIFOs. This provides the flexibility of out-of-order fetching for different traffic classes while preventing the need to store all packets from all classes simultaneously, as each FIFO only needs to store packets for its specific class.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary checks of traffic class pause status before allocating buffer space. By determining which traffic classes are active before fetching packets, the system avoids allocating buffer space for paused classes, reducing overall memory requirements while maintaining flexibility.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8248945B1System and method for Ethernet per priority pause packet flow control buffering
Publication Date: 2012.08.21 MACOM CONNECTIVITY SOLUTIONS LLC
  • US8248945B1 patent drawing
  • US8248945B1 patent drawing
  • US8248945B1 patent drawing

AI summary

A method is provided for managing a transmit buffer using per priority pause flow control. An Ethernet transceiver generates packet descriptors identifying packets to be transmitted that are stored in memory. A priority is assigned to each descriptor and associated packet. Each descriptor is loaded into a queue having a queue priority associated with the descriptor priority. In response to accessing a first descriptor, output from a selected first priority queue, a first packet associated with the first descriptor is fetched into a transmit buffer from the memory. If subsequent to fetching the first packet, a per priority flow control message is received pausing first priority packets, the first packet is flushed from the transmit buffer. Then, a second descriptor is accessed from a selected second priority queue, and a second packet associated with the second descriptor is fetched and transmitted from the transmit buffer.