Reconfigurable Ethernet Receiver AFE for Dual-Speed Automotive Links

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Solution Overview

Problem

Current in-vehicle networking technologies, such as CAN and FlexRay, face challenges in meeting the increasing bandwidth requirements of modern automotive applications, particularly with the need for both 100 Mbps and 1000 Mbps/1 Gbps Ethernet links over unshielded twisted pair copper wires while adhering to automotive EMI emission standards.

Innovation Solution

A reconfigurable Ethernet transceiver with a dual-mode analog front-end circuit that selectively switches between low data rate and high data rate signal paths, utilizing shared and upstream ADCs, and residual signal amplification to support both 100Base-T1 and 1000Base-T1 standards, optimizing power consumption and cost-effectiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate transceivers are used for 100 Mbps and 1000 Mbps Ethernet links, then each standard is supported with optimized performance, but device complexity and cost increase

Engineering Contradiction:
ImproveEthernet link supportVSAvoidtransceiver configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transceiver is designed with a reconfigurable analog front-end that can operate in multiple modes (100Base-T1 and 1000Base-T1) using the same hardware components. The AFE includes configurable ADCs, signal conditioning circuits, and filtering stages that can be dynamically adjusted to support both Ethernet standards, eliminating the need for separate transceiver devices.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The transceiver employs dynamic reconfiguration capabilities where the analog front-end parameters (such as ADC sampling rates, filter bandwidths, and signal conditioning gains) can be changed in real-time based on the detected Ethernet link speed. This allows the same hardware to adapt its characteristics to match the requirements of either 100 Mbps or 1000 Mbps operation.

Inventive Principle:
Principle #15Dynamics

2Speed

If full-power components are always active, then high data rate performance is maintained, but power consumption increases

Engineering Contradiction:
Improvedata rateVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The transceiver implements dynamic power management by adjusting the operating mode of the analog front-end based on the active Ethernet standard. When operating at 100 Mbps, the system configures the ADCs and signal processing stages to use lower power settings appropriate for the reduced data rate, while maintaining full performance capability when 1000 Mbps operation is detected or required.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters of the analog front-end components based on the Ethernet link speed. For 1000Base-T1 operation, the ADC sampling rate and signal processing bandwidth are configured to handle the higher data rate, while for 100Base-T1, these parameters are reduced accordingly, optimizing power consumption for the actual operational requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10361710B2Reconfigurable Ethernet receiver and an analog front-end circuit thereof
Publication Date: 2019.07.23 NXP BV
  • US10361710B2 patent drawing
  • US10361710B2 patent drawing
  • US10361710B2 patent drawing

AI summary

The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.