Multi-Core Ethernet Switching Chip Master-Slave Information Synchronization
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Solution Overview
Problem
Current Ethernet switching chips with a single IP core cannot meet the high message processing bandwidth requirements due to limitations in clock frequency, necessitating the design of dual or multiple IP core chips, but existing methods fail to optimize information processing effectively across multiple cores.
Innovation Solution
Implementing a master-slave mode in Ethernet switching chips with multiple IP cores, where the master IP core receives information processing requests, updates global and dedicated tables, and synchronizes information with slave IP cores, ensuring consistent message processing without conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single IP core is used in the Ethernet switching chip, then the device complexity is low, but the message processing bandwidth cannot meet the requirements of up to 25.6 Tbps
Solution Approach 1:
The patent divides the single IP core into multiple IP cores (dual-core or multi-core configuration) to increase message processing bandwidth. Each IP core operates independently with its own global information table, allowing parallel processing of multiple data streams simultaneously, thus achieving 25.6 Tbps bandwidth capability while maintaining manageable complexity through modular architecture.
2Productivity
If dual or multiple IP cores are designed in the Ethernet switching chip, then the message processing bandwidth can meet requirements, but information processing conflicts occur between cores
Solution Approach 1:
The patent segments the global information table into separate tables for each IP core (first global information table for first IP core, second global information table for second IP core). This segmentation isolates the data structures of each core, eliminating conflicts when multiple cores access and modify global information simultaneously, thus ensuring information processing consistency while maintaining high bandwidth capability.
Solution Approach 2:
The patent introduces a mediation mechanism where IP cores exchange information through defined interfaces and protocols. When one IP core needs to access information from another core's table, it does so through controlled mediation rather than direct access, preventing conflicts and ensuring data consistency across multiple cores.
3Productivity
If multiple IP cores operate independently, then processing parallelism is achieved, but system behavior becomes inconsistent with single-core expectations
Solution Approach 1:
The patent merges the behaviors of multiple IP cores to present a unified system interface that is compatible with single-core expectations. Externally, the multi-core system behaves identically to a single-core system, while internally leveraging parallel processing capabilities. This allows existing single-core protocols and interfaces to work seamlessly with the enhanced multi-core architecture.
Data Source
AI summary
An information processing method, an Ethernet switching chip and a storage medium are provided. The method includes: executing, by a master IP core, one of following operations: updating a global information table of the master IP core according to first information corresponding to the information processing request, and sending the first information to each slave IP core; updating a dedicated information table of the master IP core according to second information corresponding to the information processing request, or, sending, to a corresponding slave IP core, third information corresponding to the information processing request; or acquiring fourth information from the global information table or the dedicated information table of the master IP core based on the information processing request and sending the fourth information to a processor, or, acquiring fifth information from a corresponding slave IP core and sending the fifth information to the processor.