Ethernet Time Synchronization Using Periodic Block Timestamps

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Solution Overview

Problem

Existing Ethernet interfaces face challenges in achieving high-precision time synchronization due to uncertainties in delay caused by factors like phase differences and digital domain processing, which affect the accuracy of time transmission in communication systems.

Innovation Solution

Utilizing a periodic block, either real or virtual, as a timestamp reference to synchronize time information, compensating for uncertain delays by recording and adjusting timestamps at both transmitting and receiving ends, ensuring accurate time information transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If in-band methods are used to transmit time signals along with services, then cost is reduced and dependence on optical modules is minimized, but digital domain processing introduces uncertain delay and reduces time transmission precision

Engineering Contradiction:
Improvetime transmission precisionVSAvoiddelay uncertainty
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by recording timestamps at multiple stages (physical layer, MAC layer, digital domain processing start/end points) before the uncertain delay occurs. These pre-recorded timestamps serve as reference points to later calculate and compensate for the delay, thereby resolving the contradiction between cost-effectiveness and precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by measuring the actual delay at each digital domain processing stage and using this feedback information to adjust the timestamp calculations. The system continuously monitors and compensates for delay variations, transforming the uncertain delay into a correctable parameter that maintains time transmission precision.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If different Ethernet interfaces with various rates are used, then system adaptability is improved, but phase difference and clock domain changes cause uncertain delay

Engineering Contradiction:
Improveinterface rate adaptabilityVSAvoidtime synchronization accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent segments the timestamp recording process into multiple independent stages across different Ethernet interfaces and clock domains. Each segment records timestamps at specific points (physical layer, MAC layer, processing boundaries), allowing the system to handle different interface rates independently while maintaining overall synchronization accuracy through cumulative delay calculation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the timestamp recording and calculation parameters according to the specific rate and characteristics of each Ethernet interface. The system modifies processing parameters based on the interface type and operating speed, enabling accurate time synchronization across diverse interface rates without compromising precision.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If FIFO depth is increased to handle higher data rates, then data transmission capability is improved, but processing delay increases and time accuracy decreases

Engineering Contradiction:
Improvedata transmission rateVSAvoidtimestamp accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent records timestamps at the beginning and end of the FIFO processing period as preliminary reference points. By capturing the time state before and after the FIFO processing delay, the system can later calculate the exact processing duration and compensate for it, thereby maintaining timestamp accuracy even with increased FIFO depth for higher data rates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary timestamp records that act as mediators between the physical layer timing and the digital domain processing. These intermediary timestamps at the FIFO boundaries serve as reference markers that allow the system to measure and compensate for processing delay, decoupling the data transmission rate from the time measurement accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3748878B1Method, device and apparatus for determining time information
Publication Date: 2026.01.28 ZTE CORP
  • EP3748878B1 patent drawingFigure 1~2
  • EP3748878B1 patent drawingFigure 3~4
  • EP3748878B1 patent drawingFigure 5

AI summary

Disclosed herein is a method for determining time information, comprising: detecting a signal of a periodic code block, and recording a time stamp of the periodic code block; according to the time stamp of a periodic code block matching a time information message, determining the time at which the time information message was sent, and generating a time stamp of the time information message. Further disclosed herein are an apparatus, device and storage medium for determining time information.