Ethernet Timestamp Insertion for TDM Clock Synchronization
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Solution Overview
Problem
Ethernet networks face challenges in providing sufficient Quality of Service (QoS) for time division multiplexed (TDM) data due to jitter and data loss issues, which are not adequately addressed by existing enhancements, limiting its implementation in TDM networks like PSTN.
Innovation Solution
The introduction of Huawei-Enhanced (HE) Ethernet operational modes, including frequency-synchronized communication mode (H-Sync) and frequency-synchronized and phase-aligned communication mode (H-TDM), which utilize timestamp insertion in inter-packet gaps and an overlay synchronous timeslot scheme to ensure deterministic data transfer and stringent QoS requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ethernet packets are transported through the network with resource arbitration and buffers at the nodes, then packet delivery reliability is improved, but network complexity increases and delay increases
Solution Approach 1:
The patent extracts the clock synchronization function from the data packet transmission process by inserting timestamps in the inter-packet gaps. This separates the timing synchronization mechanism from the data payload, allowing Ethernet to provide TDM-like deterministic timing without requiring complex resource arbitration and buffering mechanisms at network nodes.
Solution Approach 2:
The patent applies preliminary action by pre-inserting clock synchronization timestamps into the inter-packet gaps before transmission. This allows receiving nodes to synchronize their clocks in advance based on these timestamps, eliminating the need for complex real-time resource arbitration and buffering that would otherwise be required to maintain deterministic delivery.
2Reliability
If Ethernet packets are transported through the network with resource arbitration and buffers at the nodes, then packet delivery reliability is improved, but delay increases
Solution Approach 1:
The patent extracts the clock synchronization function from the data packet transmission process by inserting timestamps in the inter-packet gaps. This separates the timing synchronization mechanism from the data payload, allowing Ethernet to provide TDM-like deterministic timing without requiring complex resource arbitration and buffering mechanisms at network nodes.
3Adaptability or versatility
If standard Ethernet protocol is used for TDM data transport, then network flexibility is maintained, but QoS requirements for TDM networks are not met
Solution Approach 1:
The patent merges the flexibility of standard Ethernet protocol with the deterministic timing requirements of TDM networks by overlaying a clock synchronization mechanism that uses timestamps inserted in inter-packet gaps. This combination allows Ethernet to maintain its decentralized, scalable nature while providing the precise clock synchronization needed for TDM voice traffic and other time-sensitive applications.
Solution Approach 2:
The patent makes the Ethernet protocol universal by enabling it to serve both traditional data transmission functions and TDM clock synchronization functions simultaneously. The timestamp insertion mechanism in inter-packet gaps allows the same Ethernet infrastructure to support both best-effort data traffic and deterministic TDM traffic without requiring separate specialized networks.
Data Source
AI summary
A network component comprising at least one processor configured to promote transmission of a frame from a first node to a second node, the frame comprising a first clock synchronization data, and a first frame count, wherein the first clock synchronization data and the first frame count are used to synchronize a first clock in the first node and a second clock in the second node. Also disclosed is a method comprising processing a frame comprising an Ethernet control symbol that delineates the beginning of the frame, a first clock synchronization data, a first frame count, and a second clock synchronization data. Included is an Ethernet node comprising at least one processor configured to synchronize a clock using a clock synchronization data comprising a first timestamp, a first frame count, a second timestamp, and a second frame count.