Ethernet Trigger Marker Switching for Adaptive Lane and FEC Control
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Solution Overview
Problem
Higher-speed Ethernet interfaces face challenges in reducing power consumption due to rare user data transmission and high latency introduced by strong forward error correction (FEC) schemes, which waste system resources and are difficult to manage, especially when no user data is transmitted.
Innovation Solution
The method involves sending a first bit stream over N logical lanes, followed by a trigger marker group to switch the processing mode, and then a second bit stream over P logical lanes, allowing for adjustable power consumption and latency by changing the number of logical lanes and FEC encoding schemes, ensuring bit-error-free transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strong forward error correction (FEC) scheme is used for encoding and decoding bit streams, then data transmission reliability is improved, but transmission latency increases and system resources are wasted
Solution Approach 1:
The patent applies dynamics by making the FEC encoding scheme adjustable rather than fixed. The system can dynamically switch between different FEC schemes (e.g., RS(544,514) for high reliability, RS(256,239) for lower latency) based on actual transmission conditions and service requirements, allowing optimization between reliability and latency trade-offs
Solution Approach 2:
The patent changes the parameters of the FEC encoding scheme by allowing selection of different coding rates and block sizes. By adjusting these parameters, the system can adapt to different transmission scenarios, reducing latency when strong error correction is not needed while maintaining reliability when required
2Productivity
If a higher-speed Ethernet interface is used to provide services for more users, then bandwidth and service capacity are improved, but power consumption cannot be reduced effectively because user data transmission rarely occurs
Solution Approach 1:
The patent implements dynamic adjustment of the number of logical lanes based on actual traffic conditions. When traffic demand is low, the system reduces the number of active logical lanes to save power while maintaining the capability to scale up to full bandwidth when needed, enabling effective power management in higher-speed Ethernet interfaces
Solution Approach 2:
The patent makes the Ethernet interface multi-functional by enabling it to operate at different speeds and configurations (different numbers of logical lanes) within the same physical interface. This allows the interface to adapt to varying service requirements and traffic patterns, providing both high bandwidth capability and low power consumption modes
3Use of energy by moving object
If the number of logical lanes is changed to adjust transmission rate and reduce power consumption, then power consumption is reduced, but transmission mode switching must be accurate and bit-error-free
Solution Approach 1:
The patent applies preliminary action by sending trigger marker groups before actual data transmission when switching between different numbers of logical lanes. These trigger markers prepare the receiving end for the upcoming transmission mode change, ensuring synchronized and accurate switching without bit errors
Solution Approach 2:
The patent uses trigger marker groups as intermediaries to facilitate smooth transitions between different transmission modes. These markers act as signaling mechanisms that coordinate the switching process between transmitting and receiving ends, ensuring bit-error-free mode changes
Data Source
AI summary
A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.