Ethertype-Based Receive FIFO Allocation for Multi-Core CPU Data Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing communication devices with multi-core CPUs face challenges in quickly accessing and processing reception data due to inefficient data allocation methods, leading to prolonged processing times.
Innovation Solution
A communication device with a multi-core CPU that includes a received frame processing unit to determine Ethertype and allocate data, and a plurality of buffering memories to store and transmit reception interrupt signals to corresponding CPUs, allowing CPUs to acquire data size and process reception data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is allocated by a data allocation unit based on Ethertype, then network function requirements are satisfied, but the time required for modules to access and process the allocated data cannot be shortened
Solution Approach 1:
The patent segments the buffering memory into multiple independent buffer regions, each dedicated to a specific Ethertype. This segmentation allows each CPU to directly access its designated buffer without contention, reducing access time while maintaining the ability to handle multiple network functions simultaneously. The buffer management unit allocates specific buffer regions to specific Ethertypes, enabling parallel processing across multiple CPUs.
Solution Approach 2:
The patent implements preliminary action by pre-allocating buffer regions for different Ethertypes before data arrival. The buffer management unit prepares the memory structure in advance with designated areas for each Ethertype, so that when data arrives and is allocated by the data allocation unit, the receiving CPU can immediately access the pre-prepared buffer region without additional allocation delays.
2Productivity
If multiple modules process different Ethertypes, then processing performance is improved, but coordination and data access efficiency between modules decreases
Solution Approach 1:
The patent applies local quality by assigning specific Ethertype handling capabilities to specific CPU modules. Each CPU is designated to process specific Ethertypes stored in its associated buffer region, creating a localized processing architecture. This reduces coordination complexity because each CPU operates independently on its assigned Ethertypes without needing to coordinate with other CPUs, while still achieving high processing performance through parallel operation of multiple specialized CPUs.
Data Source
AI summary
The time required for each CPU of a multi-core CPU to end access of reception data after receiving data is shortened. A communication device includes a multi-core CPU implemented with CPUs configured to implement an application; a received frame processor configured to determine an Ethertype of reception data and allocate the reception data according to the Ethertype; and a plurality of receive FIFOs configured to receive the reception data allocated by the received frame processing unit and store the reception data according to the Ethertype. Each of the receive FIFOs is configured to transmit a reception interrupt signal to a corresponding CPU of the multi-core CPU when receiving the reception data. The CPU that receives the reception interrupt signal acquires a data size of the reception data from the receive FIFO that transmits the reception interrupt signal and performs processing of reading the reception databased on the data size.