Embedded Time-of-Day Receiver for Stable Second DPLL Lock
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Solution Overview
Problem
In embedded Time of Day (eTod) systems, the time delay in decoding phase difference information between clock reference signals can lead to instability and noise in the second digital phase locked loop (DPLL), especially when the carrier clock frequency is low, causing prolonged lock times and potential instability.
Innovation Solution
The proposed solution involves using extrapolation or interpolation methods to adjust the phase difference between clock reference signals, combined with low-pass filtering, to stabilize the second DPLL without introducing extra wander and noise, by generating a recovered second signal that is phase locked to the local clock within the receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If direct decoding of phase difference information is used, then the system structure is simple, but the second DPLL becomes unstable and noisy at low carrier clock frequencies
Solution Approach 1:
The patent applies preliminary action by decoding the phase difference information one frame early before it is needed for the current frame. This allows the second DPLL to receive pre-processed, stabilized phase difference data in advance, preventing instability and noise issues that would occur with direct real-time decoding at low carrier clock frequencies.
2Loss of time
If phase difference information is decoded in real-time, then the lock time is short, but the second DPLL experiences noise and wander
Solution Approach 1:
By decoding phase difference information one frame early, the system prepares stable reference data in advance. This preliminary decoding allows the second DPLL to lock quickly while using pre-processed data that has already been optimized, thereby achieving both short lock time and low noise/wander performance.
Solution Approach 2:
The patent introduces an intermediary processing step where phase difference information from one frame is decoded and prepared before being used in the next frame. This intermediary decoded value acts as a mediator that smooths out noise and wander, allowing the second DPLL to operate cleanly while maintaining rapid lock capability.
3Reliability
If extrapolation or interpolation is used to generate phase difference, then DPLL stability improves, but system complexity increases
Solution Approach 1:
The patent uses preliminary decoding of phase difference information from the previous frame as a foundation for generating stable phase difference values. By having the decoded value ready in advance, the system can apply simple extrapolation or interpolation algorithms with minimal computational overhead, improving DPLL stability without significantly increasing system complexity.
Data Source
AI summary
In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.