Die-Side ETS Package Substrate Layout for CTE and Warpage Balance
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Solution Overview
Problem
The mismatch in metal density between the die-side ETS metallization layer and other metallization layers in IC packages causes a coefficient of thermal expansion (CTE) mismatch, leading to warpage and increased risk of voids in solder joints due to asymmetric metal distribution.
Innovation Solution
A supplemental metal layer with additional interconnects is coupled to the die-side ETS metallization layer to increase metal density and thickness, reducing the need to reduce thickness in other layers, thereby balancing metal density and CTE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded metal traces are used in the die-side ETS metallization layer to provide higher density bump/solder joints with reduced line/spacing ratio, then the electrical interface density to the die is improved, but the metal density becomes asymmetric compared to other metallization layers, causing CTE mismatch and warpage
Solution Approach 1:
The patent applies local quality by adding supplemental metal specifically to the die-side ETS metallization layer where metal density is deficient. This localized metal supplementation (through additional metal traces, wider traces, or ground planes) balances the metal density in that specific region without affecting other metallization layers, thereby resolving the CTE mismatch and warpage caused by asymmetric metal distribution while maintaining the high-density electrical interface provided by the embedded metal traces.
2Area of moving object
If the area of embedded metal traces in the die-side ETS metallization layer is reduced to achieve reduced line/spacing ratio, then the bump/solder joint density is improved, but the metal area becomes less than other metallization layers, exacerbating metal density mismatch
Solution Approach 1:
The patent merges the function of the embedded metal traces with additional supplemental metal structures in the die-side ETS metallization layer. By combining the high-density embedded traces with supplemental metal traces, wider traces, or ground planes, the total metal area and metal density are increased to match other metallization layers, thereby compensating for the reduced individual trace area achieved through reduced line/spacing ratio.
3Stability of the object's composition
If metal density is increased in the die-side ETS metallization layer by adding supplemental metal, then the CTE mismatch is reduced, but the device complexity increases due to additional metallization layers
Solution Approach 1:
The patent applies parameter changes by modifying the metal density parameter in the die-side ETS metallization layer through supplemental metal additions. This changes the physical parameter (metal density) to achieve CTE balance with other metallization layers. The complexity increase is managed by implementing the supplemental metal in integrated ways (additional traces, wider traces, or ground planes) that work within the existing metallization layer structure rather than requiring entirely new complex architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces metal density mismatch and CTE imbalance, minimizing warpage and void formation in solder joints, ensuring stable and reliable electrical connections.
Implementation Method 1
a supplemental metal layer with additional interconnects is coupled to the die-side ETS metallization layer to increase metal density and thickness
Implementation Method 2
This approach reduces metal density mismatch and CTE imbalance, minimizing warpage and void formation in solder joints
Data Source
AI summary
Integrated circuit (IC) packages employing a supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch, and related fabrication methods. An IC package includes a semiconductor die (“die”) electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer adjacent to and coupled to the die. To reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, a supplemental metal layer with additional metal interconnects is disposed adjacent to the die-side ETS metallization layer. The additional metal interconnects are coupled in a vertical direction to the embedded metal traces in the die-side ETS metallization layer to increase metal density of die-side metal interconnects formed by the additional metal interconnects coupled to the embedded metal traces in the die-side ETS metallization layer.