ETSOI CMOS with In-Situ Doped Source and Drain
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Solution Overview
Problem
The challenge in manufacturing extremely thin semiconductor on insulator (ETSOI) devices is to reduce silicon loss from photolithography and etching processes while avoiding damage to the thin SOI layer, and to recrystallize the amorphized layer without causing excessive dopant diffusion, which is incompatible with state-of-the-art CMOS technology.
Innovation Solution
A method is introduced that forms ETSOI CMOS devices using a single photoresist mask and introduces dopants into extension regions by diffusion from epitaxially formed raised source and drain regions, reducing silicon loss and avoiding damage to the thin SOI layer by using a single masking step and selective epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography and etching processes are used to form source and drain regions, then doping precision is improved, but silicon loss increases and the thin SOI layer is damaged
Solution Approach 1:
The patent performs preliminary doping during the epitaxial growth of source and drain regions, before the final etching step. By incorporating dopants into the silicon material during growth, the doping is accomplished in advance, eliminating the need for subsequent ion implantation steps that would require multiple photolithography and etching cycles. This preliminary action reduces silicon loss while achieving the required doping precision.
2Stability of the object's composition
If high temperature annealing is performed to recrystallize the amorphized SOI layer, then crystallization is achieved, but excessive dopant diffusion occurs
Solution Approach 1:
The patent changes the processing parameters by performing doping during low-temperature epitaxial growth rather than through high-temperature ion implantation and annealing. The dopants are incorporated at growth temperatures (typically 600-900°C) during the formation of source and drain regions, avoiding the need for high-temperature annealing that would cause excessive dopant diffusion. This parameter change achieves both crystallization and precise dopant distribution.
3Manufacturing precision
If conventional ion implantation is used to dope source and drain regions, then doping control is improved, but the thin SOI layer is damaged and requires high temperature annealing
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical epitaxial growth process. Instead of physically bombarding the silicon with ions, dopants are incorporated chemically during the epitaxial growth of source and drain regions. This substitution eliminates the mechanical damage to the thin SOI layer that occurs during ion implantation, while still achieving precise doping control through the growth process parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces silicon loss and prevents damage to the thin SOI layer, enabling the formation of ETSOI CMOS devices with improved electrical characteristics without the need for high temperature annealing, which is incompatible with current CMOS technology.
Implementation Method 1
The dopant from the second conductivity in-situ doped second semiconductor material and the first conductivity in-situ doped first semiconductor material is then diffused into the first semiconductor layer to form extension regions
Implementation Method 2
A first conductivity in-situ doped first semiconductor material is formed on exposed surfaces of the first portion of the first semiconductor layer adjacent to the first gate structure, and on exposed surfaces of the second portion of the first semiconductor layer adjacent to the second gate structure
Data Source
AI summary
A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.