ETSOI pFET Strain via Base Substrate Oxidation
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Solution Overview
Problem
It is challenging to apply compressive strain to the channel region of p-type field effect transistors (pFETs) formed on extremely-thin semiconductor-on-insulator (ETSOI) substrates due to the thinness of the top semiconductor layers, as conventional strain techniques like stress liners and embedded silicon-germanium source/drain regions are ineffective.
Innovation Solution
A method is developed to form a strained channel region in an ETSOI substrate by etching the SOI and buried oxide (BOX) layers to create recess regions, followed by oxidation of the base substrate to form oxide regions that apply compressive strain to the channel region, thereby enhancing strain application to pFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional compressive strain techniques (stress liners and embedded silicon-germanium source/drain regions) are applied to ETSOI pFETs, then device performance should be improved, but the techniques prove ineffective due to the extreme thinness of the top semiconductor layer
Solution Approach 1:
The patent transitions from applying strain within the plane of the thin SOI layer to applying strain from the vertical dimension by oxidizing the base substrate beneath the channel. This creates oxide regions that expand vertically and laterally, inducing compressive strain in the channel region from below, bypassing the limitation of the thin top layer thickness.
Solution Approach 2:
The patent introduces oxide regions formed by base substrate oxidation as an intermediary mechanism to transmit compressive strain to the channel. These oxide regions act as a mediator that converts the volume expansion during oxidation into mechanical compressive stress on the overlying SOI channel, enabling strain application without direct contact with the thin top layer.
2Reliability
If the top semiconductor layer thickness is reduced to achieve superior short channel control and device matching, then device performance is improved, but the ability to apply compressive strain to pFETs is reduced
Solution Approach 1:
The patent applies strain from the vertical dimension by oxidizing the base substrate beneath the channel, rather than attempting to apply strain laterally within the constrained thin SOI layer. This dimensional shift allows effective strain application regardless of the top layer thickness.
Solution Approach 2:
The patent changes the physical state and volume of the base substrate through oxidation, transforming it into oxide regions with different mechanical properties. This parameter change (volume expansion during oxidation) directly generates compressive strain in the channel region, adapting the strain application method to work with extremely thin top layers.
3Reliability
If dopant concentration is increased to maintain device performance as transistors shrink, then device performance is maintained, but carrier mobility is reduced due to increased scattering
Solution Approach 1:
The patent changes the crystal lattice structure of the channel region through compressive strain induced by oxide region expansion. This parameter change modifies the band structure and carrier scattering mechanisms, enhancing carrier mobility even at higher dopant concentrations by reducing phonon scattering and improving carrier transport.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively applies compressive strain to pFETs on ETSOI substrates, improving device performance by reducing parasitic capacitance and enhancing carrier mobility, which is crucial for maintaining performance as transistors shrink in size.
Implementation Method 1
The base substrate below the first recess region and the second recess region may be oxidized to form a first oxide region in the first recess region and a second oxide region in the second recess region
Data Source
AI summary
Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.