ETSOI Transistor Nitride Oxide Liner Spacer
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Solution Overview
Problem
Extremely Thin Silicon-On-Insulator (ETSOI) transistors with high-K dielectric and metal gate stacks face issues with underoxide growth, which lowers gate capacitance, and silicon loss during spacer formation, leading to high series resistance and low on current.
Innovation Solution
A thin spacer structure comprising nitride and oxide layers is used to prevent underoxide growth and silicon loss, enabling the integration of a high-K dielectric and metal gate stack with epitaxial raised source/drain regions, where a nitride liner and oxide liner are formed to stop nitride RIE and prevent silicon consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If oxide spacers are used in high-K dielectric transistors, then transistor structure is formed, but underoxide growth occurs which lowers gate capacitance
Solution Approach 1:
A nitride liner layer is introduced as an intermediary between the oxide spacer and the high-K dielectric. This nitride layer acts as a barrier that prevents oxygen diffusion, thereby stopping underoxide growth while still allowing the oxide spacer to provide its structural function for transistor formation.
Solution Approach 2:
The spacer structure is segmented into multiple functional layers: an oxide spacer for structural definition, a nitride liner for preventing underoxide growth, and a cap oxide layer for protection. Each layer performs a specific function, resolving the contradiction between structure formation and gate capacitance maintenance.
2Manufacturing precision
If nitride RIE is used to form self-aligned sidewall spacers, then alignment precision is improved, but silicon loss occurs leading to high series resistance
Solution Approach 1:
An oxide liner layer is introduced as a protective intermediary between the nitride spacer and the silicon surface. This oxide layer acts as an etch stop during nitride RIE, preventing silicon loss while still allowing the nitride spacer to provide self-aligned sidewall formation with high precision.
Solution Approach 2:
The oxide liner is formed in advance before nitride spacer deposition. This preliminary protective layer prevents silicon loss during subsequent nitride RIE processing, ensuring that the self-aligned sidewall spacers are formed with high precision without causing harmful silicon loss.
3Reliability
If raised source/drain is formed to reduce series resistance, then on current increases, but silicon loss during spacer formation reduces effectiveness
Solution Approach 1:
The oxide liner serves as a protective intermediary that prevents silicon loss during nitride spacer formation. This ensures that the raised source/drain regions maintain their intended dimensions and doping profiles, maximizing their effectiveness in reducing series resistance without being compromised by silicon loss.
Solution Approach 2:
The oxide liner is formed in advance to protect the silicon surface before any spacer formation processes. This preliminary protection ensures that when raised source/drain regions are subsequently formed, the silicon is not lost during spacer fabrication, preserving the low series resistance characteristic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents underoxide growth and silicon loss, maintaining high gate capacitance and reducing series resistance, thereby enhancing transistor performance by increasing on current and maintaining low off current.
Implementation Method 1
a nitride liner 1140 and an oxide liner 1242 are formed over the ETSOI layer 106 and the gate stack 722
Implementation Method 2
the formation of a raised source/drain also requires the use of spacers for selective epitaxial growth, which leads to silicon loss during reactive-ion etching ("RIE") of the spacer
Implementation Method 3
The high-K dielectric and metal gate stack also increases the gate capacitance (CG), which leads to a higher transistor on current (IDSAT)
Implementation Method 4
any thin-body SOI transistor like an ETSOI transistor needs an epitaxial raised source/drain to obtain a low transistor series resistance
Data Source
AI summary
An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.