ETSOI Logic Memory Hybrid Chip Weight Reduction
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Solution Overview
Problem
The weight of the handle substrate in silicon on insulator (SOI) substrates contributes significantly to the total weight of electronic systems, and there is a need to reduce this weight while maintaining the functionality of semiconductor and memory devices.
Innovation Solution
A method is provided for forming logic circuitry and memory devices on an extremely thin semiconductor on insulator (ETSOI) substrate, where a handle substrate is removed after processing, and interconnect wiring connects the logic device with the memory device, allowing for the reduction of the handle substrate's weight and integration of both devices on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If a handle substrate is used in silicon on insulator (SOI) substrates, then structural support and processing stability are maintained, but the total weight of electronic systems increases significantly
Solution Approach 1:
The patent removes the handle substrate from the final device structure after it has served its purpose during processing. The handle substrate is extracted and discarded, leaving only the thin semiconductor layer with the desired devices, thereby eliminating the weight penalty while maintaining structural support during critical processing stages
Solution Approach 2:
The patent divides the substrate structure into functional segments: a temporary handle substrate for processing support, a thin active semiconductor layer for device formation, and a release layer for separation. This segmentation allows the handle substrate to be removed after serving its temporary purpose, reducing overall weight
2Device complexity
If logic devices and memory devices are formed separately on different substrates, then each device can be optimized independently, but the overall device complexity and interconnection requirements increase
Solution Approach 1:
The patent combines logic devices and memory devices on the same thin semiconductor substrate, allowing them to share common processing steps and interconnect structures. This merging reduces overall device complexity and manufacturing steps while both device types can still be independently designed and optimized through separate device formation regions
3Weight of moving object
If the semiconductor layer is made extremely thin to reduce weight, then weight reduction is achieved, but manufacturing precision and device reliability become more challenging
Solution Approach 1:
The patent performs preliminary bonding of the thin semiconductor layer to a handle substrate before device fabrication. This preliminary action provides mechanical support during subsequent processing steps, enabling precise manufacturing on extremely thin layers that would otherwise be too fragile to handle
Solution Approach 2:
The handle substrate acts as an intermediary during processing, providing mechanical support and stability to the extremely thin semiconductor layer. The release layer serves as another intermediary, enabling clean separation after processing without damaging the thin active layer
4Adaptability or versatility
If interconnect wiring is formed to connect logic devices with memory devices, then device functionality is enhanced, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the interconnect formation process for both logic and memory devices into unified processing steps. Since both device types are on the same substrate, common interconnect layers and patterning steps can serve both device types, reducing overall manufacturing complexity while enabling full functionality
Data Source
AI summary
A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.