Execution Unit Accelerator for Programmable Graphics Format Support
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Solution Overview
Problem
Graphics processing units (GPUs) lack flexibility in executing instructions for new formats, requiring significant time to incorporate new video formats due to the need for programming associated logic into EU hardware.
Innovation Solution
An accelerator is implemented in the execution unit pipeline to perform programmable operations, enabling faster execution of graphics pipelines and supporting new formats without the need for hardware modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware logic is programmed into EU hardware to support new video formats, then the GPU can execute the new format, but it takes several years to incorporate and the hardware structure becomes more complex
Solution Approach 1:
The patent introduces an intermediary component called an 'accelerator' that mediates between the execution unit and the new video format requirements. This accelerator is a separate hardware module that can be dynamically configured to support new formats without modifying the core EU hardware, thus resolving the contradiction between adaptability and device complexity
Solution Approach 2:
The patent segments the GPU architecture into distinct functional components: the execution unit (EU) for general-purpose processing and the accelerator for format-specific operations. This segmentation allows the accelerator to be independently configured and updated for new video formats without affecting the stable EU hardware design, thereby maintaining simplicity while achieving versatility
2Adaptability or versatility
If hardware logic is programmed into EU hardware to support new video formats, then the GPU can execute the new format, but it takes several years to incorporate
Solution Approach 1:
The patent implements dynamic configurability in the accelerator, allowing it to be reconfigured through software programming to support different video formats. This dynamic approach eliminates the need for lengthy hardware redesign cycles, enabling rapid adaptation to new formats while maintaining the speed of hardware execution
Solution Approach 2:
The accelerator is pre-configured with the capability to load and execute format-specific logic through its programmable interface. By preparing the accelerator in advance with the ability to load new format handlers, the system can quickly adopt new video formats without waiting for hardware reconfiguration, thus reducing the time to incorporation
3Productivity
If an accelerator is added to the execution unit pipeline to enable programmable operations, then execution speed increases and flexibility improves, but the device complexity increases
Solution Approach 1:
The accelerator is designed as a universal programmable module that can handle multiple video formats and processing tasks through software configuration. This multi-functionality allows a single accelerator unit to replace what would otherwise require multiple dedicated hardware components, achieving high productivity while limiting the increase in device complexity
Solution Approach 2:
Instead of creating entirely new hardware circuits for each video format, the patent uses the accelerator to load and execute software copies or emulations of format-specific processing logic. This approach achieves format support through software instantiation rather than hardware duplication, thereby improving execution speed for new formats without proportionally increasing physical device complexity
Data Source
AI summary
A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.