eUICC Error Recovery via Clock Signal Reset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In serial communication systems involving eUICC, the absence of a reset pin and shared power lines can lead to deadlocks where the eUICC loses the ability to receive protocol commands, making it difficult to reset the protocol state machine, especially when physical resets are not feasible without damaging other components.
Innovation Solution
The method employs the serial clock signal to provide a reset signal by varying clock parameters such as frequency, duty cycle, or amplitude to transition the eUICC from an error state to a reset state, allowing the protocol to resume without a physical reset pin or power supply manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset pin is used to reset the eUICC from error state, then the protocol state machine can be reset, but the system requires additional pins and physical reset infrastructure
Solution Approach 1:
The patent merges the reset function with the existing clock signal line by embedding reset commands within the clock signal sequence. Instead of using a separate reset pin, the system combines the reset functionality with the clock signal that already connects the reader and eUICC, thereby eliminating the need for additional physical infrastructure while maintaining error recovery capability
Solution Approach 2:
The clock signal line is given multiple functions: it serves both as the regular clock signal for data transmission and as a carrier for reset commands. By making the clock signal multi-functional, the system achieves reset capability without requiring a dedicated reset pin, thus reducing device complexity while preserving reliability
2Reliability
If power supply manipulation is used to reset the eUICC, then the protocol state machine can be reset, but other components sharing the power line may be damaged
Solution Approach 1:
The patent segments the reset function from the power supply system by implementing reset through the clock signal line instead. This segmentation allows the reset operation to be performed independently on the eUICC without affecting other components that share the common power line, thereby eliminating the harmful effects while maintaining protocol reset capability
Solution Approach 2:
The clock signal line acts as an intermediary carrier for the reset command. Instead of directly manipulating the power supply to reset the eUICC, the system uses the clock signal as an intermediate medium to transmit the reset instruction, thereby achieving the desired effect without exposing shared components to damaging power fluctuations
3Productivity
If the serial interface is shared between multiple devices, then resource utilization is improved, but error state in one device blocks the interface for other devices
Solution Approach 1:
The eUICC performs self-diagnosis and self-reset by monitoring its own error states and automatically executing reset sequences through the clock signal line when errors are detected. This self-service capability allows the device to recover from errors autonomously without blocking the shared interface, thereby maintaining both high utilization efficiency and continuous availability
Solution Approach 2:
The system implements feedback mechanisms where the reader monitors the communication status with the eUICC and detects error states. Upon detecting an error, the reader triggers appropriate reset sequences through the clock signal line, creating a closed-loop control system that maintains interface availability while preserving shared resource utilization
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
Method to recover an error state (E) in a serial communication with an integrated circuit card (12), in particular an eUICC (12), where a serial communication protocol includes a transition from said error state (E) to a reset state (R) upon reception of a reset signal (RS) by said integrated circuit card (12), said serial communication including operating on a serial communication interface (12a) comprising at least a serial clock signal line (SCK) coupling a transmitter device (11) and said integrated circuit card (12) and on which a clock signal (CKS) is transmitted from the transmitter device (11) to said integrated circuit card (12), said method including, upon detection (210) of an error state (E), embedding (220) at the transmitter device said reset signal in a serial clock signal (SCK) sent to the integrated circuit card (12) as reference clock signal on said serial clock signal line (CKS), said reset signal being represented by a variation (VC) of parameters of the clock signal, checking (230, CC) the presence of said variation (VC) of parameters of the clock signal at the integrated circuit card (12), upon checking (CC) the presence of said variation (VC) of parameters of the clock signal at the integrated circuit card (12) performing (235) said transition from an error state (E) to a reset state (R).