eUSB2 Repeater Vcm Precharge for Stable SOP Detection
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Solution Overview
Problem
USB repeaters face challenges in accurately detecting and transmitting the start of packet (SOP) indicators due to instability caused by center tap capacitance, especially in eUSB2 systems, which can lead to jitter and truncation of data bits, and existing solutions like CDR or PLL circuits are costly and power-intensive.
Innovation Solution
A circuit that precharges the common mode voltage (Vcm) node by activating a switch or using a combination of capacitors to mitigate capacitance effects, allowing accurate SOP detection and transmission within 4 unit intervals without requiring a CDR or PLL, thus reducing space and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If CDR or PLL circuits are used to detect and transmit SOP indicators, then detection accuracy is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent extracts and removes the CDR and PLL circuits from the USB repeater design. By eliminating these complex frequency synchronization circuits, the invention achieves SOP detection without requiring precise clock recovery, thereby reducing power consumption and device complexity while maintaining detection accuracy through alternative timing mechanisms.
Solution Approach 2:
The patent replaces expensive, complex CDR/PLL circuits with simpler, lower-cost alternative circuitry that uses basic timing circuits and threshold detection. This substitution uses less powerful but sufficient components that consume less energy and reduce overall system complexity while achieving the required SOP detection function.
2Measurement precision
If CDR or PLL circuits are used to detect and transmit SOP indicators, then detection accuracy is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent extracts and removes the CDR and PLL circuits from the USB repeater design. By eliminating these complex frequency synchronization circuits, the invention achieves SOP detection without requiring precise clock recovery, thereby reducing power consumption and device complexity while maintaining detection accuracy through alternative timing mechanisms.
Solution Approach 2:
The patent integrates multiple functions into simpler circuit blocks. The timing circuit performs both SOP detection and packet synchronization functions that would traditionally require separate CDR and PLL circuits. This functional integration reduces overall device complexity and component count while maintaining detection accuracy.
3Device complexity
If center tap capacitance is present in eUSB2 systems, then circuit design is simplified, but SOP detection stability deteriorates due to jitter and data bit truncation
Solution Approach 1:
The patent applies preliminary anti-action by introducing a timing circuit that anticipates and compensates for the instability caused by center tap capacitance. The timing circuit generates predetermined timing signals that pre-establish reference points for SOP detection, counteracting the jitter and timing variations introduced by the capacitance before they can affect detection accuracy.
Solution Approach 2:
The patent performs preliminary action by establishing timing references and synchronization signals before actual SOP detection occurs. The timing circuit generates advance timing signals that prepare the detection circuitry for incoming packets, ensuring stable detection despite the presence of center tap capacitance by pre-synchronizing the system state.
Data Source
AI summary
At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.