Eutectic Bonding Pad Insulation for MEMS Wafer Test

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Solution Overview

Problem

Wafer acceptance test (WAT) failures occur due to bonded pads connecting with each other during eutectic bonding in MEMS sensors, resulting in short circuits and test structure failures.

Innovation Solution

A test structure manufacturing method involving a top wafer and a bottom wafer with spaced pads, where at least one side surface of adjacent pads has an insulation layer, and trenches on the pads to prevent pad connection during bonding, using materials like silicon oxide, silicon nitride, or silicon oxynitride, and forming these structures to ensure proper spacing and insulation for effective bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If eutectic bonding is performed on top wafer and bottom wafer without insulation layers, then bonding strength is improved, but adjacent pads become connected causing short circuits

Engineering Contradiction:
Improvebonding strengthVSAvoidelectrical isolation
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The pad structure is segmented into multiple parts: the pad body, side insulation layers, and top insulation layers. This segmentation allows the pad to maintain electrical connectivity through the bonding interface while preventing lateral electrical connection between adjacent pads through the insulating layers on the sides and top surfaces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulation layers are introduced as intermediary elements between adjacent pads. These layers (comprising silicon oxide, silicon nitride, and silicon oxynitride) act as electrical barriers that prevent short circuits while allowing the bonding process to proceed effectively.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If insulation layers are added on pad side surfaces, then electrical isolation between pads is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulation layer formation process is merged with the existing pad fabrication process. The same deposition and etching equipment and procedures used for creating the pad structures are utilized to form the insulation layers, thereby integrating multiple functions into a unified process flow and minimizing additional complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If insulation layers and trenches are formed on pads, then WAT test failure rate is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improvetest pass rateVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The insulation layers are formed on the pad side surfaces and top surfaces before the eutectic bonding process. This preliminary action ensures that electrical isolation is established in advance, preventing potential short circuits during bonding and eliminating the need for additional isolation steps after bonding, thereby simplifying the overall manufacturing sequence.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents adjacent pads from connecting after bonding, thereby mitigating WAT test failures and ensuring valid test results by maintaining pad separation and improving bonding efficiency.

Implementation Method 1

bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad

Methodology Applied
Scientific EffectEutectic bonding:

Data Source

PatentUS10600700B2Test structure and manufacturing method therefor
Publication Date: 2020.03.24 SEMICON MFG INT (SHANGHAI) CORP
  • US10600700B2 patent drawing
  • US10600700B2 patent drawing
  • US10600700B2 patent drawing

AI summary

This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.