EUV Patterning Air Gap Formation in Semiconductor Interconnects
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturization and reducing off-state capacitance at advanced technology nodes, particularly with conductive line widths less than 25 nanometers, as existing methods for forming air gaps are inaccurate and damaging, and cannot be employed at nodes with pitches of 25-35 nanometers and 15-20 nanometer spacings due to overlay limitations and aggressive etching techniques.
Innovation Solution
The method involves forming an air gap in a dielectric interconnect layer using extreme ultraviolet (EUV) light and a high etch selectivity dielectric layer, such as silicon nitride with hydrogen, to create openings less than 10 nanometers, allowing for precise patterning and deposition of an air gap capping layer, which reduces off-state capacitance by controlling the effective dielectric constant of the interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current photolithography processes (193 nm light) are used to form air gap openings, then the process is simple and cost-effective, but the overlay limitations prevent accurate patterning of openings smaller than 10 nm
Solution Approach 1:
The patent replaces conventional 193 nm photolithography with EUV (extreme ultraviolet) lithography to achieve the required sub-10 nm patterning precision. This substitution of the lighting system enables accurate formation of air gap openings at advanced technology nodes while maintaining process feasibility
Solution Approach 2:
The patent changes the wavelength parameter of the light source from 193 nm to EUV range, which enables the formation of smaller features (5-10 nm openings) with sufficient precision. This parameter change resolves the overlay limitations of conventional photolithography
2Manufacturing precision
If aggressive etching techniques are used to form air gaps, then the air gap formation is achieved, but the conductive interconnect structure is damaged
Solution Approach 1:
The patent introduces a high etch selectivity dielectric layer as an intermediary between the low-K dielectric layer and the conductive interconnect. This intermediary layer has etch selectivity between 15:1 and 30:1, allowing selective removal to form air gaps while protecting the underlying conductive interconnect from damage
Solution Approach 2:
The patent applies different etch selectivity properties to different dielectric layers. The high etch selectivity dielectric layer is specifically engineered to be highly selective to the low-K dielectric, enabling localized removal of material to create air gaps without affecting adjacent conductive structures
3Reliability
If air gaps are formed to reduce off-state capacitance, then the dielectric constant is improved, but the manufacturing precision requirements become extremely challenging at pitches of 25-35 nm
Solution Approach 1:
The patent forms the high etch selectivity dielectric layer over the low-K dielectric layer before patterning the air gap openings. This preliminary action creates a protective structure that enables subsequent precise patterning and selective removal to form air gaps with accurate placement and dimensions
Solution Approach 2:
The high etch selectivity dielectric layer serves as a mediator that enables precise air gap formation. It allows for controlled removal of low-K dielectric material to create air gaps with widths of no greater than 15 nm, achieving the required manufacturing precision for advanced technology nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of air gaps with widths of no greater than 15 nanometers, effectively reducing off-state capacitance and improving performance at advanced technology nodes, while maintaining the integrity of the conductive interconnects, and allows for more precise via placement and metal layer integration.
Implementation Method 1
patterning the air gap mask layer preferably using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening
Implementation Method 2
etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer
Implementation Method 3
forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space
Data Source
AI summary
A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.