EUV Circuit Design with 2D and 1D Layer Segmentation
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Solution Overview
Problem
Integrated circuits with smaller feature sizes face challenges in maintaining production yield and economic viability due to increased complexity, requiring advanced lithographic techniques like EUV technology to achieve finer feature sizes and higher functionality.
Innovation Solution
The design incorporates a first layer with two-dimensional shapes and a second layer with one-dimensional shapes, featuring a shared drain terminal and source terminal termination, optimized for EUV technology, using materials like copper and cobalt or tungsten, to improve manufacturability and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If smaller feature sizes are used to increase functionality, then device density and functionality are improved, but production yield degrades
Solution Approach 1:
The patent transitions from conventional two-dimensional circuit layouts to a three-dimensional stacked architecture with multiple layers (first layer with 2D shapes, second layer with 1D shapes). This vertical stacking enables higher device density and functionality without proportionally increasing the manufacturing complexity of individual features, thereby improving functionality while maintaining production yield.
Solution Approach 2:
The circuit is divided into multiple layers with distinct geometric characteristics - the first layer contains two-dimensional shapes while the second layer contains one-dimensional shapes. This segmentation allows each layer to be optimized independently for its specific manufacturing process and functional requirements, enabling higher overall functionality without compromising the manufacturability of individual layers.
2Manufacturing precision
If advanced lithographic techniques like EUV are used to achieve finer feature sizes, then feature size precision is improved, but manufacturing complexity increases
Solution Approach 1:
By moving to three-dimensional stacked architecture, the patent achieves finer effective feature sizes through vertical stacking rather than solely relying on reducing lateral dimensions via advanced lithography. This approach obtains manufacturing precision benefits while avoiding the full manufacturing complexity burden of extreme miniaturization in a single layer.
Solution Approach 2:
Different layers are assigned different geometric qualities - the first layer uses two-dimensional shapes optimized for certain manufacturing processes, while the second layer uses one-dimensional shapes optimized for other processes. This local optimization allows each layer to be manufactured with appropriate precision using suitable techniques, reducing overall manufacturing complexity while achieving fine feature sizes.
3Adaptability or versatility
If more functionality is incorporated in the same physical volume, then device density is improved, but production yield degrades
Solution Approach 1:
The patent incorporates more functionality in the same physical volume by stacking multiple layers vertically. The first layer with two-dimensional shapes and the second layer with one-dimensional shapes can be manufactured using optimized processes for each layer type, maintaining production yield while achieving higher device density and functionality through the third dimension.
Data Source
AI summary
Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes two-dimensional (2D) shapes; a second layer coupled adjacent to the first layer through at least one via hole, wherein the second layer includes only one-dimensional (1D) shapes; a shared drain terminal; and a source terminal termination.