EUV Gate Patterning for Varying Lengths and Consistent Pitch
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Solution Overview
Problem
Existing technologies face challenges in forming large arrays of semiconductor devices with varying gate lengths, leading to increased complexity and cost due to the need for multiple fabrication steps and potential asymmetry in gate pitch.
Innovation Solution
Utilizing extreme ultraviolet (EUV) lithography to pattern gate structures with varying gate lengths using a single mask, maintaining a consistent gate pitch and achieving gradual transitions between different gate lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple fabrication steps are used to form semiconductor devices with different gate lengths, then device versatility is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into multiple gate portions (first gate portion, second gate portion, third gate portion) with different gate lengths formed in a single lithography step. Each gate portion corresponds to different semiconductor regions, allowing diverse device configurations without additional fabrication steps.
Solution Approach 2:
A single gate structure serves multiple functions by incorporating gate portions of different lengths to accommodate various device types (e.g., memory devices, logic devices) within the same array. The gate structure can be selectively extended or truncated to match different channel region configurations.
2Adaptability or versatility
If multiple fabrication steps are used to form semiconductor devices with different gate lengths, then device versatility is improved, but manufacturing cost increases
Solution Approach 1:
Multiple gate structures with different lengths are merged into a single continuous gate structure formed by one lithography pattern. The gate structure includes first, second, and third gate portions that can be simultaneously patterned, eliminating the need for separate fabrication steps for each gate length variation.
Solution Approach 2:
The unified gate structure design allows a single fabrication process to produce multiple device types with different gate lengths, reducing per-device manufacturing cost while maintaining versatility.
3Adaptability or versatility
If gate pitch is varied to accommodate different gate lengths, then device customization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate structure exhibits local variations in length while maintaining uniform pitch across the entire array. Different gate portions have different lengths tailored to specific device requirements, but all gates are positioned at consistent intervals, preserving pitch uniformity throughout the semiconductor array.
4Adaptability or versatility
If additional fabrication steps are used to form different gate lengths, then device functionality is improved, but productivity decreases
Solution Approach 1:
The gate structure is divided into functional segments (gate portions) with different lengths that can be simultaneously formed in one lithography step, enabling diverse device functionality without sacrificing manufacturing speed or requiring additional processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication complexity and cost while maintaining a consistent gate pitch, enabling efficient production of semiconductor devices with varying gate lengths.
Implementation Method 1
As further described below, an extreme ultraviolet (EUV) process may be used to directly pattern the shape of the gate having the varying gate lengths
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~2D
AI summary
Techniques are provided herein to form semiconductor devices having different gate lengths yet maintaining a substantially similar pitch between gates. A row of semiconductor devices having semiconductor regions extending in a first direction can include some devices having a first gate length in the first direction and some devices having a second gate length in the first direction, where the second gate length is greater from the first gate length (e.g., by 2 nm or more). According to some embodiments, a given gate structure that extends in a second direction substantially orthogonal to the first direction can have its gate length transition between the first gate length and the second gate length at a region between adjacent semiconductor regions along the second direction. When observed in a plan view, the second gate length extends beyond both sides of the first gate length along the first direction.