EUV Gate Patterning With Variable Gate Lengths at Constant Pitch
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Solution Overview
Problem
The challenge in forming large arrays of semiconductor devices is the difficulty in scaling down memory and logic cells, particularly due to technology limitations in lithography, which makes it hard to form semiconductor devices with different gate lengths while maintaining a consistent gate pitch.
Innovation Solution
The techniques involve using an EUV patterning process to directly pattern gate structures with varying gate lengths in an array, allowing for a single mask to be used and maintaining a consistent gate pitch of less than 80 nm, thereby simplifying the fabrication process and reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used to form semiconductor devices with different gate lengths, then multiple additional fabrication steps are required, but this increases device complexity and manufacturing cost
Solution Approach 1:
The patent uses EUV lithography to change the patterning parameters, enabling direct formation of gates with different lengths (L1 and L2) in a single process step. The extreme ultraviolet light allows for precise control of gate length variations without requiring multiple fabrication steps, thus resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The gate structure is segmented into different length portions (first gate portion with length L1, second gate portion with length L2) within a single continuous gate line. This segmentation is achieved through direct EUV patterning, allowing different gate lengths to coexist without increasing overall process complexity
2Manufacturing precision
If multiple fabrication steps are used to form devices with different gate lengths, then gate pitch consistency becomes difficult to maintain, but this increases loss of time and productivity
Solution Approach 1:
The gate line is formed with preliminary defined segments of different lengths using EUV patterning before any subsequent processing steps. This preliminary action ensures that the different gate lengths are established in a single step, maintaining consistent gate pitch while avoiding the time loss associated with multiple fabrication steps
Solution Approach 2:
The patent merges the formation of different gate lengths into a single EUV patterning step rather than using separate steps for each gate length. This combining of operations maintains gate pitch consistency while significantly improving fabrication throughput by eliminating redundant processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with different gate lengths while maintaining a consistent gate pitch, which is essential for efficient integration of logic and memory cells, thereby improving the scalability and cost-effectiveness of chip fabrication.
Implementation Method 1
an extreme ultraviolet (EUV) process may be used to directly pattern the shape of the gate having the varying gate lengths
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having different gate lengths yet maintaining a substantially similar pitch between gates. A row of semiconductor devices having semiconductor regions extending in a first direction can include some devices having a first gate length in the first direction and some devices having a second gate length in the first direction, where the second gate length is greater from the first gate length (e.g., by 2 nm or more). According to some embodiments, a given gate structure that extends in a second direction substantially orthogonal to the first direction can have its gate length transition between the first gate length and the second gate length at a region between adjacent semiconductor regions along the second direction. When observed in a plan view, the second gate length may extend beyond both sides of the first gate length along the first direction.