Semiconductor Patterning with EUV Key Layout for Narrow-Pitch Reliability
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Solution Overview
Problem
The high integration of semiconductor devices leads to reduced reliability due to increased complexity and smaller line widths, which existing methods struggle to address effectively.
Innovation Solution
The method involves forming semiconductor devices using extreme ultraviolet (EUV) lithography to create landing pads and key patterns with precise control over pitch and distance, preventing process defects and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high integration is implemented to increase device functionality, then device complexity increases, but reliability decreases
Solution Approach 1:
The patent applies segmentation by dividing the formation of closely spaced patterns into multiple sequential steps: first forming a mandrel pattern, then forming a spacer pattern around it, and finally forming a second pattern. This multi-stage approach allows each step to be optimized independently, maintaining precision even as overall device integration increases.
Solution Approach 2:
The patent uses preliminary action by first forming the mandrel pattern and spacer pattern before forming the final target pattern. The mandrel and spacer serve as preliminary structures that define the positions and dimensions of subsequent patterns, ensuring precise placement before the actual functional structures are created.
2Productivity
If line widths are decreased to increase integration density, then manufacturing precision requirements increase, but process defects increase
Solution Approach 1:
The patent introduces intermediary structures (mandrels and spacers) that mediate between the lithography process and the final pattern formation. These intermediaries act as templates that transfer patterns with high fidelity, allowing precise control of final line widths without directly exposing them to the limitations of single-step lithography.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional structured patterning by forming vertical spacer structures around mandrels. This dimensional transition enables precise control of horizontal pattern dimensions through vertical structure geometry, improving manufacturing precision for closely spaced features.
3Reliability
If photolithography process margin is increased to reduce defects, then manufacturing complexity increases, but process time increases
Solution Approach 1:
The patent employs periodic action by using a repeating sequence of deposition and etching steps to form alternating mandrel and spacer patterns. This rhythmic alternation of material addition and removal allows systematic creation of complex patterns through simple, repeatable process modules, reducing overall process time despite increased precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the process margin in photolithography, reduces the risk of defects, and enhances the reliability of electrical connections between landing pads and contacts, thereby improving the overall reliability of semiconductor devices.
Implementation Method 1
forming semiconductor devices using extreme ultraviolet (EUV) lithography
Data Source
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AI summary
Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target layer (MTL) on a substrate (SUB) including cell (CER) and key (KER) regions, forming lower (LML) and upper (UML) mask layers on the etching target layer (MTL), performing photolithography to form an upper mask pattern including a hole (LHO) on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench (TR4) between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.