EUV Mask Ordering via Correlation Parameter Prediction
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Solution Overview
Problem
Current EUV patterning processes face challenges in predicting the process window accurately, leading to unsuitable mask structures being ordered, resulting in patterning defects and wasteful expenditure due to the inability of existing methods to reliably correlate simulation results with actual wafer results.
Innovation Solution
A method using a processor to determine a correlation parameter based on simulated depth of focus, energy latitude, line-edge roughness area, and width parameters, generating a predicted wafer process window to assess the suitability of a mask structure for ordering, thereby preventing the use of unsuitable masks in the EUV patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simulation results are used to determine mask structure ordering, then productivity is improved by avoiding unnecessary mask orders, but measurement precision deteriorates because existing methods cannot accurately predict actual wafer results
Solution Approach 1:
The patent transforms multiple simulation parameters (DOF, EL, LER area, LER width) into a single composite correlation parameter CP using a mathematical formula with weighting values. This parameter transformation enables accurate prediction of wafer results from simulation data, resolving the precision issue while maintaining productivity benefits
Solution Approach 2:
The correlation parameter CP acts as an intermediary between simulation results and actual wafer outcomes. By introducing this intermediate metric that combines multiple simulation parameters, the system can accurately predict whether masks will produce defects without directly testing actual wafers, thus maintaining both productivity and precision
2Measurement precision
If multiple simulation parameters are combined into a correlation parameter, then measurement precision is improved by accurately predicting wafer results, but device complexity increases due to additional computational processing
Solution Approach 1:
The patent merges multiple simulation parameters (DOF, EL, LER area, LER width) into a single correlation parameter CP through a unified mathematical formula. This consolidation improves prediction accuracy while actually reducing computational complexity by combining multiple assessments into one comprehensive metric rather than analyzing each parameter separately
3Device complexity
If existing prediction methods are used, then device complexity is kept simple, but loss of information occurs because simulation results do not correlate with actual wafer results
Solution Approach 1:
The patent applies parameter transformation by converting multiple simulation metrics into a weighted correlation parameter CP that specifically captures the relationship between simulation and actual wafer results. This parameter change preserves information that would otherwise be lost, enabling accurate prediction while maintaining relative method simplicity
Solution Approach 2:
The correlation parameter CP provides feedback on the quality of simulation-wafer correlation. By calculating CP and comparing it against threshold values, the system determines whether simulation results are reliable for mask ordering decisions, preventing information loss about prediction reliability
Data Source
AI summary
A method for determining whether to order a mask structure using a processor may include acquiring a simulation result of an EUV pattern layout, determining a correlation parameter (CP), generating a predicted wafer process window, and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window. The processor may determine the CP based on a weighting value and a simulated depth of focus (DOF), a simulated energy latitude (EL), and simulated line-LER area and LER-width parameters in the simulation result. The CP may indicate a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout. The predicted wafer process window may be generated using the processor based on the CP. The predicted wafer process window may indicate whether the actual wafer result of the EUV pattern layout will include a patterning defect.