EUV Lithography Overlay Analysis Using Augmented Orthogonal and Radial Coordinates
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Solution Overview
Problem
The increasing complexity of memory device operations and structures due to reduced memory cell sizes in high integration information communication devices requires improved precision and reliability in overlay measurement and analysis for EUV lithography, which existing technologies have not adequately addressed.
Innovation Solution
A method for manufacturing semiconductor devices that involves transferring and patterning shots on wafers using EUV lithography, with internal and external shots, measuring and analyzing overlays, and applying augmented overlays in orthogonal and radial directions to improve overlay precision and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EUV lithography is used for high integration memory devices, then manufacturing precision is improved, but measurement precision of overlay is insufficient
Solution Approach 1:
The wafer surface is divided into multiple regions (first region, second region, third region) with different overlay analysis methods applied to each. Internal shots within critical radius use one analysis approach while external shots use another, allowing optimized measurement precision for each zone while maintaining overall manufacturing precision.
Solution Approach 2:
The patent introduces a new dimension of analysis by creating augmented overlays that include both measured overlay data and artificially generated overlay data. This multi-dimensional approach combines actual measurements with simulated data to enhance measurement precision beyond what single-point measurements can provide.
2Reliability
If overlay measurement is performed on all shots, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
Different regions of the wafer receive different levels and types of overlay analysis. The first region (internal shots) receives standard overlay measurement, while the second region (external shots) receives augmented overlay analysis. This localized approach improves reliability where needed without uniformly increasing complexity across the entire manufacturing process.
Solution Approach 2:
Instead of performing complete overlay measurements on all shots, the patent applies partial measurement strategies where augmented overlays are generated only for specific external shots. This selective application maintains reliability for critical areas while reducing overall process complexity.
3Measurement precision
If augmented overlays are provided to external shots, then overlay precision is improved, but data processing complexity increases
Solution Approach 1:
Augmented overlays are generated in advance before final overlay analysis. By pre-calculating and storing augmented overlay data for external shots, the system prepares precise measurement data ahead of time, reducing real-time processing complexity while maintaining high overlay precision.
Solution Approach 2:
The patent introduces augmented overlays as an intermediary data structure that bridges raw measurement data and final overlay analysis. This intermediate representation simplifies the processing pipeline by organizing data in a format that facilitates precise analysis while managing computational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and manufacturing yield of semiconductor devices by providing precise overlay measurements and corrections, improving the accuracy of EUV lithography processes.
Implementation Method 1
transferring a circuit pattern on an extreme ultraviolet (EUV) photomask to a photoresist layer formed on a wafer
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes transferring an internal shot and an external shot by performing a patterning process on a first wafer, analyzing an overlay of the first wafer, and performing a lithography process on a second wafer, based on the analyzing of the overlay of the first wafer, wherein the analyzing of the overlay of the first wafer includes providing, to the first region, first augmented overlays generated based on an orthogonal coordinate system using first and second directions perpendicular to each other as an axis, and providing, to the second region, second augmented overlays that are overlays in a radial direction from the center of the first wafer.