EUV Resist Capping and Divot Filling for Smoother Etching

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Solution Overview

Problem

Extreme Ultraviolet (EUV) lithography faces challenges in reducing roughness and improving etch selectivity of EUV resists, leading to undesirable roughness and insufficient etch selectivity in semiconductor fabrication, particularly at advanced technology nodes like 16 nm and beyond.

Innovation Solution

The method involves descumming, divot filling, and protecting EUV resists by treating the semiconductor substrate with halogen-containing plasmas, selectively depositing silicon-containing precursors, and forming silicon oxide caps or amorphous carbon caps to enhance etch selectivity and smoothness of features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If EUV lithography is used to pattern thin films at advanced technology nodes, then resolution is improved, but roughness in the photoresist increases due to stochastic effects

Engineering Contradiction:
ImproveresolutionVSAvoidroughness
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent applies preliminary descumming treatment to the EUV resist before the main etching process. This involves removing carbonaceous material (scum) that forms on the resist surface during EUV lithography exposure and development. By performing this cleaning action beforehand, the subsequent etching process produces smoother features with reduced line edge roughness and line width roughness, thus resolving the contradiction between achieving high resolution and maintaining surface smoothness

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If EUV lithography photoresist materials are used, then resolution at 30 nm scale is achieved, but etch selectivity to the underlying layer becomes insufficient

Engineering Contradiction:
ImproveresolutionVSAvoidetch selectivity
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces an intermediary protective layer (such as a silicon oxide layer or other dielectric material) between the EUV resist and the underlying metal oxide layer. This intermediary layer serves as a buffer that enhances the etch selectivity, allowing the EUV resist to maintain its resolution capabilities while the intermediary layer protects the underlying layer during etching, thus resolving the contradiction between resolution and etch selectivity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the photoresist is directly etched without protective measures, then process complexity is reduced, but line edge roughness and line width roughness increase

Engineering Contradiction:
Improveprocess complexityVSAvoidline edge roughness
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary protective coating to the EUV resist features before etching. A thin layer of protective material is deposited on the resist surface to prevent direct etching damage. This preliminary protection action, combined with controlled etching parameters, achieves smooth line edges and reduced roughness while maintaining acceptable process complexity through automation and standardization of the protective coating step

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in smoother EUV resist features and increased selectivity, improving the quality of etched patterns and preventing defects in semiconductor devices by reducing line edge roughness and line width roughness, thereby enhancing process yield and device performance.

Implementation Method 1

treating the exposed portion of the metal oxide layer with a halogen-containing plasma

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

selectively depositing a silicon-containing precursor on carbon-containing features

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 3

selectively depositing a silicon-containing precursor

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 4

treating the silicon-containing precursor to convert the silicon-containing precursor to a silicon oxide cap

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 5

exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas to remove the modified scum

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS12062538B2Atomic layer etch and selective deposition process for extreme ultraviolet lithography resist improvement
Publication Date: 2024.08.13 LAM RES CORP
  • US12062538B2 patent drawing
  • US12062538B2 patent drawing
  • US12062538B2 patent drawing

AI summary

Provided herein are methods and systems for reducing roughness of an EUV resist and improving etched features. The methods involve descumming an EUV resist, filling divots of the EUV resist, and protecting EUV resists with a cap. The resulting EUV resist has smoother features and increased selectivity to an underlying layer, which improves the quality of etched features. Following etching of the underlying layer, the cap may be removed.