Event Bus Arbiter for Multicore SoC Inter-Processor Communication

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Solution Overview

Problem

In Systems-on-Chip (SoC) with multiple processors and peripheral circuits, existing bus systems like AHB and APB require complex software routines for inter-processor communication, leading to increased complexity and difficulty in meeting real-time requirements, as only one processor can control signal flow across the bus, stalling other functional units during simultaneous access.

Innovation Solution

Implementing an event bus with an arbiter and frame encoder/decoder at each subsystem's terminal, allowing direct communication between functional units without processor intervention, enabling point-to-point and point-to-multipoint connections, and reducing software complexity by eliminating the need for processor-managed bus communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If AHB and APB bus systems are used for inter-processor communication, then communication between functional units can be established, but software complexity increases and real-time requirements become difficult to fulfill due to the need for processor-controlled signal flow

Engineering Contradiction:
Improvereal-time capabilityVSAvoidsoftware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the bus control function from the processor and implements it in dedicated hardware (bus matrix with arbiters). This removes the burden of bus management from the processor software, reducing software complexity while maintaining reliable real-time communication through hardware-controlled signal flow arbitration.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a bus matrix as an intermediary component between processors and peripherals. This bus matrix includes arbiters that automatically manage signal flow and coordinate access requests, eliminating the need for processor-controlled communication protocols while ensuring reliable real-time data transmission.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If AHB and APB bus systems are used for communication, then functional units can exchange data, but only one functional unit can access the bus at a time, causing other units to be stalled

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidbus access delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic bus arbitration through hardware arbiters in the bus matrix that can handle multiple access requests simultaneously. The arbiters dynamically allocate bus access rights based on priority and timing, allowing multiple functional units to communicate efficiently without stalling, thereby improving productivity while minimizing access delays.

Inventive Principle:
Principle #15Dynamics

3Reliability

If processor-controlled bus communication is used, then data transmission can be managed, but the processor must execute software routines for controlling signal flow, increasing complexity

Engineering Contradiction:
Improvecommunication controlVSAvoidsoftware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/software-based bus control system with a hardware-based bus matrix containing dedicated arbiters. This substitution eliminates the need for processor-executed software routines, reducing software complexity while maintaining reliable communication control through hardware-level signal flow management.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20240385911A1Inter Processor Communication using an Event Bus in Multicore Systems-on-Chip
Publication Date: 2024.11.21 INFINEON TECHNOLOGIES AG
  • US20240385911A1 patent drawing
  • US20240385911A1 patent drawing
  • US20240385911A1 patent drawing

AI summary

One embodiment relates to a multi-code system. The system includes a first subsystem and (at least) a second subsystem, each including an event bus terminal and a processor core. The system further includes an event bus comprising an event bus controller and a plurality of bus lines for connecting the first subsystem and the second subsystem with the event bus controller. The event bus controller includes an arbiter configured to arbitrate data transmission across the bus lines. The event bus terminal of each subsystem includes a first queue for outgoing data provided by the respective processor core and a frame encoder that is configured to read the outgoing data from the first queue and transmit it to the event bus controller. The event bus terminal of each subsystem further includes a frame decoder that is configured to receive incoming data from the event bus controller and to write at least a portion of the incoming data into a selected one of data sinks wherein the selection is made based on the received data.