Event Controlled Decoding Circuit Using Memory-Based Waveform Generation
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Solution Overview
Problem
Existing event controlled decoding circuits face challenges in adapting to changes in output signal generation and exhibit complexity in logic design, particularly as the number of inputs/outputs increases, leading to sub-optimal performance.
Innovation Solution
The proposed circuit includes a time counter, memory for storing signal transition times, a comparator for matching counter values with stored times, and an address counter to increment addresses in memory, enabling the generation of output signal waveforms with logic state values dependent on received data bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a logic circuit is used to decode control inputs and generate output signals, then the circuit can perform decoding operations, but the complexity in logic design increases as the number of inputs/outputs increases
Solution Approach 1:
The patent uses a memory circuit to store pre-defined output signal patterns instead of using complex logic circuits to generate them in real-time. The memory circuit acts as a lookup table that stores copies of desired output waveforms, allowing the system to retrieve pre-stored patterns by addressing the memory with control inputs. This replaces complex combinatorial logic with simpler memory access operations.
Solution Approach 2:
The patent changes the approach from logic-based signal generation to memory-based signal retrieval. By storing output signal patterns in memory and accessing them through address inputs, the system transforms the problem from complex logical computation to simple memory addressing. The control inputs serve as addresses that directly index into the memory to retrieve the corresponding output patterns.
2Adaptability or versatility
If the number of inputs and outputs in the decoding circuit increases, then the circuit can handle more signals, but the logic design becomes more complex and difficult to adapt
Solution Approach 1:
The memory circuit stores pre-defined output signal patterns that can be easily modified or reprogrammed. Instead of redesigning complex logic circuits when adaptability is needed, the system simply changes the contents of the memory or the addressing scheme, making adaptation straightforward and flexible.
Solution Approach 2:
The memory-based approach provides a universal solution that can handle any number of inputs and outputs by simply changing the memory size and addressing scheme, rather than designing different logic circuits for different configurations. The same basic architecture serves multiple functions and scales easily.
3Productivity
If traditional logic circuits are used for decoding, then the circuit can generate output signals, but the logic design becomes sub-optimal as complexity increases
Solution Approach 1:
The patent stores optimal output signal patterns in memory, allowing the system to retrieve pre-optimized waveforms efficiently. This eliminates the need for complex real-time logic computation and enables faster signal generation by simply reading from memory, improving productivity while reducing logic complexity.
Solution Approach 2:
The output signal patterns are pre-computed and stored in memory before runtime. This preliminary action of pre-processing and storing the signal patterns allows the circuit to generate outputs efficiently during operation without performing complex logic operations in real-time, thereby improving signal generation efficiency.
Data Source
AI summary
A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.