Event Controller Synchronization for Multi-Core Bus Efficiency
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Solution Overview
Problem
In multi-core systems with a non-uniform memory access structure, existing synchronization methods using common variables or barriers lead to reduced processing efficiency as the number of cores increases, and message-based synchronization becomes complex, affecting overall processing efficiency.
Innovation Solution
A data processing device with multiple stages connected via a slotted bus, featuring processing elements, stage memories, and event controllers, where each stage has a data read-only bus for memory access and a data write-only bus for inter-stage communication, with an access point that stores data write history and minimizes inter-stage bus usage through event access processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronization methods using common variables or barriers are applied to multi-core systems, then processor synchronization is achieved, but processing efficiency is reduced as the number of cores increases
Solution Approach 1:
The patent introduces an event controller as an intermediary component that manages synchronization between processing elements. Instead of having multiple cores directly access and contend for common variables or barriers, the event controller receives events from processing elements and manages the synchronization protocol, thereby reducing direct contention and improving efficiency as the system scales.
Solution Approach 2:
The synchronization logic is extracted from the processing elements themselves and placed into a dedicated event controller. This separation allows processing elements to focus on their computational tasks while the event controller handles the overhead of synchronization, reducing the impact on processing efficiency.
2Adaptability or versatility
If message-based synchronization is used to effectively process asynchronous events, then event processing capability is improved, but synchronizing control becomes complicated as the number of cores increases
Solution Approach 1:
The event controller serves as a universal synchronization mechanism that handles all types of asynchronous events from multiple processing elements through a single, unified interface. This multi-functional component manages event registration, notification, and synchronization state for all cores, avoiding the need for separate complex control logic for each core pair.
Solution Approach 2:
The system changes the synchronization parameter from direct core-to-core communication to event controller-mediated communication. By parameterizing the synchronization approach through the event controller's event handling mechanisms, the system achieves adaptable asynchronous event processing without proportionally increasing control complexity.
Data Source
AI summary
A data processing device includes: data processing stages having a processing element, a stage memory and an event controller; and an inter-stage bus connecting the stages via an access point. External and process completion events are input into the controller for generating a task start event toward the processing element according to the external and process completion events. Each access point has an access table storing a data write history when the processing element writes data in the memory in a memory access process. The processing element executes an event access process indicative of memory access process completion after the processing element completes the memory access process to the memory via the access point. The access point executes another event access process for inputting the process completion event into the controller of another stage, based on the data write history when the processing element executes the event access process.