Event-Driven Digital LDO Regulator for Low Latency and Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital LDO regulators face challenges in achieving short control loop latency while maintaining low power consumption, as they often require increased power consumption to reduce control loop latency or use amplifiers that lead to high standby power consumption and instability.
Innovation Solution
An event-driven digital LDO regulator design that includes an analog-to-digital converter, a digital processor for generating control signals, and separate power transistor arrays for proportional and integral control, allowing for efficient voltage regulation with reduced control loop latency and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digital LDO regulators reduce control loop latency, then control speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the digital LDO regulator by using an event-driven architecture that activates control operations based on detected voltage variations. The system transitions between active regulation mode and standby mode, adjusting its operational state dynamically to match actual regulation needs, thereby reducing unnecessary power consumption while maintaining fast response when needed.
Solution Approach 2:
The patent employs periodic sampling of the output voltage through the ADC at controlled intervals rather than continuous monitoring. The event-driven controller triggers regulation operations only when voltage deviations are detected, creating a periodic rather than continuous operation pattern. This approach reduces average power consumption while maintaining the ability to respond quickly to actual voltage changes.
2Speed
If analog LDO regulators use amplifiers for high-speed operation, then operation speed is improved, but standby power consumption increases and stability decreases
Solution Approach 1:
The patent removes the analog amplifier component from the LDO regulator design, extracting the high-speed operation capability from the analog domain and implementing it instead in the digital domain. The digital processor handles control decisions and triggers events without requiring continuous analog amplification, thereby eliminating the standby power consumption and stability issues associated with analog amplifiers while maintaining fast response capability.
Solution Approach 2:
The patent substitutes the analog amplifier-based control mechanism with a digital event-driven control mechanism. Instead of using continuous analog signal amplification to achieve high-speed operation, the system uses digital voltage sampling, comparison, and event-triggered control signals. This substitution eliminates the need for high-power analog amplifiers in standby mode while preserving fast regulation response through efficient digital processing.
Data Source
AI summary
A regulator may comprise: an ADC unit for detecting a change in an output voltage and outputting an error code based on the detected result; a digital processing unit for generating a proportional control signal, a plurality of integral control signals, a counting signal, and an error sign signal based on the error code, outputting pull-up and pull-down control signals by multiplying the error code by a proportional gain factor in response to the proportional control signal, and outputting a plurality of sub-pull-up control signals by performing integration on the integral control signals based on the counting signal and multiplying the integration result by an integral gain factor; a first driving unit for outputting a first current in response to the pull-up and pull-down control signals; and a second driving unit for outputting a second current in response to the sub-pull-up control signals.