Event-Driven Simulation Accelerator for Hardware Design Verification
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Solution Overview
Problem
Software-based simulators for hardware design verification face inefficiencies due to memory access latency and inability to realize parallel computing benefits, while hardware emulators suffer from high compilation efforts and loss of abstraction, impacting debugging and scalability.
Innovation Solution
A simulation system with a simulation accelerator that hides memory latency and exploits parallelism by executing RTL designs and testbench models through event-driven simulation, sorting instructions into logically independent groups, and using event tables to manage pending events, thereby minimizing memory access latency and enhancing parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software-based simulators are used for hardware design verification, then debugging capabilities and abstraction are maintained, but memory access latency increases and parallel computing benefits are lost
Solution Approach 1:
The simulation system is segmented into multiple parallel simulation accelerators, each capable of independently executing simulation instructions. This segmentation enables parallel processing of design verification tasks while maintaining the debugging capabilities of software-based simulators, thereby reducing overall simulation time and memory access latency through concurrent execution.
Solution Approach 2:
The patent transitions from single-threaded sequential simulation to multi-threaded parallel simulation by adding a temporal dimension to the execution model. Multiple simulation accelerators operate simultaneously in different time threads, executing independent simulation instances in parallel, which dramatically reduces memory access latency and accelerates design verification while preserving debugging functionality.
2Productivity
If hardware emulators are used for design verification, then parallel computing benefits are realized, but compilation efforts increase and abstraction is lost
Solution Approach 1:
The patent introduces simulation accelerators as an intermediary between software-based simulators and hardware emulators. These accelerators execute compiled simulation instructions in parallel hardware environments, providing hardware-level parallel processing performance while maintaining a simplified compilation process compared to full hardware emulation, thus achieving high productivity without excessive compilation complexity.
3Device complexity
If instructions are executed sequentially in simulation, then simplicity is maintained, but simulation speed decreases
Solution Approach 1:
The instruction execution model is segmented into multiple independent parallel execution streams. Each simulation accelerator maintains a simplified sequential execution model internally, but multiple such simple executors run in parallel, collectively achieving high simulation speed while preserving the simplicity of the underlying execution architecture through modular replication.
Solution Approach 2:
The patent creates multiple copies of the simulation execution engine in the form of parallel simulation accelerators. Each copy independently executes simulation instructions sequentially with simplicity maintained, but the collective parallel operation of multiple copies dramatically increases overall simulation speed, achieving fast verification without complex execution models.
Data Source
AI summary
An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.