Event-Driven Simulation Accelerator for Hardware Design Verification
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Solution Overview
Problem
Software-based simulators for hardware design verification face inefficiencies due to memory access latency and inability to realize parallel computing benefits, while hardware emulators suffer from high compilation efforts and loss of abstraction, impacting debugging and scalability.
Innovation Solution
A simulation system with a simulation accelerator that hides memory latency and exploits parallelism by executing sorted groups of instructions with pending events, using an event table to manage instruction execution and classify events as perform or bypass, thereby accelerating RTL simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based simulators are used for hardware design verification, then debugging capabilities and abstraction are maintained, but memory access latency and inability to realize parallel computing benefits reduce simulation efficiency
Solution Approach 1:
The patent divides the simulation system into distinct components: a simulation accelerator for parallel event processing, an event table for organized event storage, and instruction sorting mechanisms. This segmentation allows the system to exploit parallelism by processing multiple events simultaneously while maintaining the debugging capabilities of software simulators.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by implementing an event-driven architecture that processes multiple instructions concurrently based on event readiness. The instruction sorting into groups enables parallel execution paths, transforming the traditional sequential simulation approach into a multi-dimensional parallel processing system that eliminates memory access bottlenecks.
2Productivity
If hardware emulators are used for hardware design verification, then simulation speed is improved, but high compilation efforts and loss of abstraction increase device complexity and reduce debugging capability
Solution Approach 1:
The patent creates a virtual simulation accelerator that replicates the parallel processing capabilities of hardware emulators through software-based event-driven execution. By copying the essential parallel execution model into a software environment with an event table and sorted instruction groups, the system achieves hardware-like simulation speed while maintaining software-based debugging capabilities and reducing compilation complexity.
3Adaptability or versatility
If all instructions are executed in software simulators, then debugging and abstraction are maintained, but memory access latency prevents realization of parallel computing benefits
Solution Approach 1:
The patent implements a dynamic instruction execution model where the simulation accelerator adaptively processes instructions based on event readiness. Instructions are sorted into groups and executed in parallel when their required events are available, creating a dynamic execution flow that maintains debugging capabilities while exploiting parallel computing opportunities as they arise during simulation.
Data Source
AI summary
An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.