Event-Driven Simulation Accelerator for Hardware Design
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Solution Overview
Problem
Software-based simulators for hardware design verification face inefficiencies due to memory access latency and inability to realize parallel computing benefits, while hardware emulators suffer from significant compilation efforts and loss of abstraction, impacting debugging and scalability.
Innovation Solution
A simulation system with a simulation accelerator that accelerates RTL simulations by hiding memory latency and exploiting parallelism, using event-driven simulation techniques to execute instructions grouped by pending events, and a dedicated simulation processor for efficient testbench-code execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based simulators are used for hardware design verification, then flexibility and debugging capabilities are maintained, but memory access latency reduces simulation speed and parallel computing benefits cannot be realized
Solution Approach 1:
The simulation system is segmented into multiple independent processing channels, each capable of executing simulation instructions in parallel. The simulation accelerator divides the simulation workload into discrete instruction streams that can be processed simultaneously across multiple channels, eliminating the single-threaded bottleneck and reducing memory access latency through parallel data retrieval and processing.
Solution Approach 2:
The patent replaces the traditional software-based simulation mechanism with a hardware-based simulation accelerator. This substitution transforms the simulation process from software execution (prone to memory latency) to hardware implementation (capable of parallel processing and reduced access times), while maintaining the flexibility of software-controlled simulation through a dedicated processor interface.
2Productivity
If software-based simulators are used, then debugging capabilities are preserved, but parallel computing benefits cannot be realized due to sequential processing limitations
Solution Approach 1:
The simulation accelerator implements dynamic instruction streaming where multiple instruction streams are processed in parallel across multiple channels. Each channel can independently execute simulation instructions, and the system dynamically manages instruction distribution and channel allocation to maximize parallel processing efficiency while maintaining debugging capabilities through the dedicated simulation processor interface.
3Speed
If hardware emulators are used, then simulation speed is improved, but significant compilation efforts are required and abstraction is lost impacting debugging and scalability
Solution Approach 1:
The simulation accelerator is designed as a universal platform that can simulate multiple different hardware designs through a standardized instruction set architecture. The dedicated simulation processor provides a unified interface for loading and executing simulation instructions, eliminating the need for separate compilation processes for each design while maintaining high simulation speed through hardware-based parallel processing.
4Adaptability or versatility
If traditional software simulators are used, then flexibility is maintained, but memory access latency significantly reduces simulation throughput
Solution Approach 1:
The dedicated simulation processor acts as an intermediary between the flexible software control interface and the high-speed hardware parallel processing units. This intermediary layer maintains adaptability by accepting standard simulation instructions while enabling throughput enhancement by distributing these instructions across multiple parallel execution channels, effectively bridging the gap between flexibility and performance.
Data Source
AI summary
An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.