Event-driven simulation accelerator for hardware design
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Solution Overview
Problem
Software-based simulators for hardware design verification face inefficiencies due to memory access latency and inability to realize parallel computing benefits, while hardware emulators suffer from significant compilation efforts and loss of abstraction, impacting debugging and scalability.
Innovation Solution
A simulation system with a simulation accelerator that accelerates RTL simulations by hiding memory latency and exploiting parallelism, using event-driven simulation and grouping instructions for parallel processing, and a dedicated simulation processor to efficiently execute testbench codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based simulators are used for hardware design verification, then debugging capabilities and abstraction are maintained, but memory access latency and inability to realize parallel computing benefits reduce simulation efficiency
Solution Approach 1:
The patent segments the instruction set into multiple groups where instructions within each group are logically independent. This segmentation enables parallel execution of different instruction groups while maintaining the debugging and abstraction capabilities of software-based simulators. The event table is also segmented into group event tables and instruction event tables to track pending events at different levels of granularity.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by organizing instructions into groups that can be executed simultaneously. The event-driven architecture adds a temporal dimension where events trigger instruction execution, allowing the simulator to process multiple instruction groups in parallel across different time steps, thereby reducing memory access latency and improving overall simulation efficiency.
2Productivity
If software-based simulators are used for hardware design verification, then debugging capabilities are maintained, but parallel computing benefits cannot be realized
Solution Approach 1:
The simulation system is segmented into distinct components: group event tables for tracking group-level pending events, instruction event tables for tracking individual instruction pending events, and multiple instruction groups for parallel execution. This segmentation enables parallel computing while maintaining a manageable system architecture that preserves debugging capabilities.
Solution Approach 2:
The event table structure acts as an intermediary mechanism that coordinates between different instruction groups and the central control logic. By using event-driven synchronization, the system enables parallel execution without requiring complex inter-group communication protocols, thus improving parallel processing capability while keeping the architecture relatively simple.
3Speed
If instructions are grouped for parallel processing, then simulation speed is improved, but system complexity increases due to event table management
Solution Approach 1:
The event table is segmented into two hierarchical levels: group event tables that track pending events at the group level and instruction event tables that track pending events at the individual instruction level. This segmentation allows the system to quickly identify which instruction groups have pending events and process them in parallel, improving simulation execution speed while managing complexity through structured organization.
Solution Approach 2:
The patent merges the functionality of tracking group-level pending events and instruction-level pending events into a unified event-driven architecture. The group event tables and instruction event tables work together as an integrated system, where group event tables provide a high-level overview and instruction event tables provide detailed tracking, thereby managing complexity through functional integration.
Data Source
AI summary
An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.