Event-Driven Shared Memory Pixels for Compact ToF Photon Counting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-of-flight (ToF) systems face challenges in efficiently utilizing memory bins for distance calculation due to layout constraints and full-well depth limitations, particularly in sub-10 μm pitch and stacked technologies, which affect cost, resolution, power consumption, and module z-height in 3D SPAD imagers.
Innovation Solution
Implementing a shared memory architecture with a shared arithmetic logic unit (ALU) and static random access memory (SRAM) among multiple pixels, utilizing a bus arbiter for event-driven access and arbitration, allowing for smaller pixel footprints and higher photon counting capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each pixel has dedicated memory bins for photon counting, then photon counting capacity and measurement precision are improved, but pixel area and device complexity increase
Solution Approach 1:
Multiple pixels share a common memory structure ( histogram bins) instead of each pixel having dedicated bins. The patent implements a shared memory architecture where photons from multiple detectors are accumulated into common histogram bins, reducing per-pixel memory requirements while maintaining distance measurement capability through centralized photon counting.
Solution Approach 2:
The shared memory bins serve multiple pixels simultaneously, making the memory structure universal rather than dedicated. A single memory resource performs the photon counting function for multiple detectors, eliminating redundant memory instances and reducing overall pixel area while preserving measurement precision through aggregated counting.
2Measurement precision
If each pixel has dedicated memory bins and incrementing circuits, then photon counting accuracy is improved, but power consumption and device complexity increase
Solution Approach 1:
Multiple pixels share a common incrementing circuit rather than each pixel having its own dedicated counter. The shared incrementing circuit updates photon counts in the shared memory bins, reducing the number of active circuits and thereby lowering overall power consumption while maintaining accurate photon counting through centralized update logic.
Solution Approach 2:
The incrementing circuit performs the photon counting function for multiple pixels through the shared memory architecture. This universal circuit replaces multiple dedicated incrementing circuits, reducing power consumption by eliminating redundant circuit operations while preserving counting accuracy through shared resource access.
3Area of moving object
If memory bins are implemented in sub-10 μm pitch pixels, then integration density is improved, but full-well depth limitations and manufacturing precision requirements increase
Solution Approach 1:
By merging memory resources across multiple pixels, the patent reduces the memory area required per pixel, enabling implementation in sub-10 μm pitch technologies. The shared memory architecture eliminates redundant storage elements, allowing sufficient functional memory capacity to fit within smaller pixel footprints while reducing sensitivity to individual cell placement variations.
Solution Approach 2:
The patent transitions from per-pixel memory allocation to a higher-level shared memory structure, effectively moving the memory organization to a different architectural dimension. This allows memory resources to be efficiently packed in the available area without the constraints of individual pixel boundaries, reducing layout precision requirements while maintaining integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient photon counting with reduced layout space and power consumption, enabling smaller pixel sizes and improved performance in ToF systems, particularly in shorter range applications.
Implementation Method 1
a plurality of detectors configured to output respective detection signals responsive to detection of a plurality of photons incident thereon
Implementation Method 2
a shared memory architecture with a shared arithmetic logic unit (ALU) and static random access memory (SRAM) among multiple pixels
Data Source
AI summary
A Time of Flight (TOF) system includes an incrementing circuit and a plurality of pixels. Each pixel includes a plurality of detectors configured to output respective detection signals responsive to detection of a plurality of photons incident thereon and a shared memory configured to store a respective count of the photons incident on each of the plurality of detectors. The incrementing circuit is configured to update the respective count for each of the plurality of detectors in the shared memory based on the respective detection signals.