Event Generating Unit for Atomic Peripheral Task Initiation
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Solution Overview
Problem
Microcontrollers face challenges in initiating multiple peripheral tasks simultaneously without interruption, as existing methods like interrupt masking or priority setting introduce complexity and are not entirely effective.
Innovation Solution
A microcontroller design featuring a processor, peripherals, a programmable peripheral interconnect, and an event-generating unit that allows for atomic initiation of multiple tasks within a predetermined time frame by storing mappings in a memory, ensuring that multiple task signals are sent simultaneously or within a very short time, eliminating the risk of interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a processor initiates multiple peripheral tasks using adjacent software instructions, then the tasks can be triggered in sequence, but the processor might receive an interrupt between triggering the first task and the second task, leading to undesirable behaviour
Solution Approach 1:
The patent introduces an event-generating unit as an intermediary component between the processor and peripherals. This unit receives a single write instruction from the processor and automatically generates multiple task initiation signals to different peripherals simultaneously, eliminating the need for complex software coordination and interrupt masking while ensuring reliable simultaneous task initiation.
Solution Approach 2:
The system segments the task initiation function by separating the processor's role (issuing a single write instruction to the event-generating register) from the actual task triggering (performed by the event-generating unit which distributes signals to multiple peripherals). This segmentation allows the processor to remain simple while the event-generating unit handles the complexity of simultaneous multi-peripheral activation.
2Reliability
If interrupt masking or priority setting is used to mitigate interruption risks, then task initiation reliability improves, but software complexity increases
Solution Approach 1:
The event-generating unit serves as a hardware intermediary that eliminates the need for software-based interrupt masking or priority management. By capturing the processor's write instruction and immediately distributing task signals to multiple peripherals in a single atomic operation, it provides reliable task initiation without requiring complex software protocols.
Solution Approach 2:
The patent replaces the mechanical/software approach of sequential instruction execution with potential interrupt interference with a hardware-based event-generating unit that performs simultaneous task initiation through electrical signal distribution. This substitution of hardware mechanism for software control eliminates the complexity of interrupt masking while ensuring atomic task initiation.
3Adaptability or versatility
If multiple processor write instructions are used to initiate peripheral tasks, then task initiation flexibility increases, but the risk of interruptions between instructions increases
Solution Approach 1:
The patent merges multiple task initiation operations into a single atomic event by having the processor write to a single event-generating register. The event-generating unit then distributes this single event to multiple peripherals simultaneously, combining what would require multiple separate processor instructions into one unified operation that cannot be interrupted.
Solution Approach 2:
The event-generating unit is pre-configured with mappings between the event-generating register and multiple peripheral tasks. When the processor writes to the register, the pre-established connections allow immediate simultaneous triggering of all mapped tasks without requiring the processor to issue multiple separate instructions, thus maintaining both flexibility and reliability.
Data Source
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AI summary
A microcontroller (2) has a processor (6), peripherals (18, 20, 22, 24, 26), a programmable peripheral interconnect (PPI) (10), an event-generating unit (EGU) (17), and a memory (8). The peripherals respond to task signals from the PPI. The EGU responds to a predetermined change to the contents of an event-generating register (57, 59) by signalling an event to the PPI. Stored PPI mappings can map an EGU event to a task of one of the peripherals. Mappings from one EGU event to two or more peripheral tasks cause the PPI to respond to an event signal from the EGU by sending the respective task signals within a maximum time limit. Software in the memory comprises instructions to store such mappings in a mapping memory, and to make the predetermined change to the contents of the event-generating register. In another aspect, an interrupt-generating unit (17) is arranged to send an interrupt to the processor (6) in response to receiving a task signal from the PPI (10).