Event Hardware Reduction in Compute-Near-Memory Processors
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Solution Overview
Problem
Existing computer architectures face significant challenges in data movement between processors and memory, leading to performance and energy constraints, which can be addressed by leveraging memory-centric compute topologies and compute-near-memory systems to enhance compute efficiency and workload throughput.
Innovation Solution
Implementing compute-near-memory systems with specialized processors and accelerators, utilizing a hybrid threading processor and fabric to facilitate high-bandwidth, low-latency operations, and employing event management circuitry with atomic processing to perform reduction operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is moved between processors and memory using conventional architectures, then data access is possible, but significant time and energy are required
Solution Approach 1:
The patent merges memory and compute operations by implementing compute-near-memory systems where reduction operations are performed directly within the memory device. This integration eliminates the need to move data between separate processors and memory, thereby reducing both data access time and energy consumption associated with data transfer.
Solution Approach 2:
The patent introduces specialized reduction logic and event hardware as intermediary components within the memory device that can perform compute operations locally. These intermediaries enable reduction operations to be executed near the data without requiring full data movement to external processors, thus reducing time and energy overhead.
2Productivity
If shared memory is used for data storage and access, then data sharing is enabled, but performance and capacity are constrained by data movement overhead
Solution Approach 1:
The patent combines memory storage and compute operations into a unified compute-near-memory architecture. By performing reduction operations directly within the memory device, the system eliminates the sequential data movement steps that constrain productivity in conventional shared memory systems, thereby improving workload throughput.
Solution Approach 2:
The patent segments the compute and memory functions into distinct but closely integrated components. The memory device contains specialized reduction logic that can operate independently on stored data, allowing compute operations to be performed in parallel with memory operations rather than requiring sequential data movement, thus enhancing productivity.
3Productivity
If reduction operations are performed using conventional processors, then computation is possible, but overhead from shared memory allocation reduces efficiency
Solution Approach 1:
The patent implements self-service compute operations where the memory device performs reduction operations on its own stored data using integrated reduction logic. This eliminates the need for external processors to allocate and manage shared memory for compute operations, thereby improving compute efficiency by removing memory allocation overhead while maintaining operational simplicity.
Data Source
AI summary
System and techniques for performing a reduction operation using event hardware are described herein. In an environment in which sub-processes are run on different processors, and these sub-processes inform a head process via event messaging, when a reduction operation is completed by a sub-process of the sub-processes, the partial result of the sub-process is received at event management circuitry of the processor of the head process. The event management circuitry uses the partial result to update an incremental result to the reduction operation as each sub-process result event message is received.