Event Link Controller for Sequential Circuit Module Control
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Solution Overview
Problem
Conventional interrupt control techniques are inefficient in speeding up data processing and reducing the load on central processing units, particularly in data processors with sequential control operations, leading to lower overall system efficiency.
Innovation Solution
The introduction of an event link controller that generates start control signals based on event control information, allowing for sequential operation of circuit modules without the need for save and return processes or priority level control, thereby reducing CPU intervention and enabling parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt control technique is used to respond to events, then the system can handle various interrupt causes with priority levels, but it takes time for arbitration and save processes before interrupt processing starts
Solution Approach 1:
The patent segments the interrupt response function into two parts: the interrupt controller handles arbitration and identification of interrupt causes, while the CPU handles the actual interrupt processing. This segmentation allows the CPU to avoid involvement in time-consuming arbitration processes, thereby reducing the time until interrupt processing starts while maintaining reliable interrupt response capability.
Solution Approach 2:
The interrupt controller performs preliminary actions by identifying the accepted cause of interrupt and preparing the interrupt request before involving the CPU. This preliminary identification and preparation work done by the interrupt controller reduces the time the CPU needs to spend on interrupt response, allowing faster start of interrupt processing.
2Productivity
If frequent interrupt processes occur to handle events, then the system can respond to multiple events, but the load on the central processing unit increases
Solution Approach 1:
The patent extracts the interrupt arbitration and identification functions from the CPU and assigns them to the interrupt controller. This extraction allows the CPU to focus only on executing interrupt service routines while the interrupt controller handles the overhead of managing multiple interrupt sources, thereby reducing CPU load while maintaining the ability to respond to frequent events.
Solution Approach 2:
The interrupt controller performs self-service by autonomously managing interrupt arbitration, identification, and request generation without requiring CPU intervention for these tasks. This self-service capability allows the system to handle multiple events efficiently while minimizing the energy consumption and load on the CPU.
3Ease of operation
If sequential control operation executes interrupt processes one after another, then the system can maintain simple control flow, but the overall data processing efficiency remains lowered
Solution Approach 1:
The interrupt controller serves as an intermediary between multiple interrupt sources and the CPU. It manages the complex interactions and arbitration between different interrupt causes, presenting a simplified interface to the CPU. This intermediary role maintains simple control flow for the CPU while enabling efficient parallel handling of multiple events, thereby improving overall data processing efficiency.
Data Source
AI summary
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.