Event Logging Module Arbitration for Bus Contention

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Solution Overview

Problem

In computing devices, the simultaneous access to a real-time clock and memory by both the controller and processor leads to contention and delays, potentially causing event data loss due to shared bus constraints, especially when the clock and memory have slow operating speeds.

Innovation Solution

An event logging module with separate command storage and arbitration mechanisms for the controller and processor, allowing concurrent access to the real-time clock and memory, thereby relieving the controller and processor of waiting times and preventing data loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the controller and processor simultaneously access the real-time clock and memory, then the system can process events efficiently, but contention and delays occur due to shared bus constraints

Engineering Contradiction:
Improveevent processing efficiencyVSAvoidaccess delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the command processing system into separate command storage buffers for the controller and processor, allowing concurrent command accumulation without interference. This segmentation enables each component to access shared resources (real-time clock and memory) independently through dedicated pathways, eliminating bus contention while maintaining efficient event processing.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If the controller and processor share access to the real-time clock and memory, then hardware resources are optimized, but data loss may occur due to contention

Engineering Contradiction:
Improvehardware resource sharingVSAvoidevent data integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces command storage buffers as intermediary structures between the controller/processor and the shared real-time clock and memory resources. These buffers act as mediators that decouple the concurrent access requests from the shared resources, allowing multiple components to queue commands independently while ensuring orderly execution that prevents data loss and maintains integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If separate command storage is implemented for controller and processor, then concurrent access is enabled, but device complexity increases

Engineering Contradiction:
Improvewaiting timeVSAvoidcommand storage structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges the command storage functionality into integrated buffers that are physically or logically combined with the existing controller and processor architectures. By incorporating the command storage within the existing hardware framework rather than adding completely separate external memory structures, the solution enables concurrent access while minimizing the increase in overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9015516B2Storing event data and a time value in memory with an event logging module
Publication Date: 2015.04.21 UTIMACO INC
  • US9015516B2 patent drawing
  • US9015516B2 patent drawing
  • US9015516B2 patent drawing

AI summary

Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command storage, clock command storage, and memory command storage.