Event-Processing Microprocessor Asynchronous Power Reduction
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Solution Overview
Problem
Conventional microprocessors face limitations in reducing power consumption due to the need for complex controls and increased capacitive load from global clocks, and they often re-operate unnecessarily to handle interrupts, leading to additional power consumption and larger circuit sizes.
Innovation Solution
A microprocessor based on an event-processing instruction set with an event controller and event register that selectively suspends or re-activates operations based on internal or external events, using an asynchronous circuit design to minimize power consumption by avoiding global clocks and unnecessary operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional microprocessors use global clocks and DVFS techniques to reduce power consumption, then power consumption is reduced to some extent, but the microprocessor still requires complex control mechanisms and cannot fully eliminate power consumption during waiting periods
Solution Approach 1:
The patent extracts and removes the global clock mechanism from the microprocessor system. By eliminating the global clock, the system removes the source of continuous power consumption and the associated complex control mechanisms for voltage and clock rate adjustment. The microprocessor operates asynchronously, with each circuit module having its own local clock or operating without a clock, thereby taking out the problematic global clock component while maintaining operational functionality.
Solution Approach 2:
The patent segments the monolithic microprocessor into multiple independent circuit modules, each capable of autonomous operation. This segmentation allows each module to operate independently with its own timing mechanism or without a clock, eliminating the need for global clock synchronization and associated complex control systems. The segmented architecture enables fine-grained power management where only active modules consume power.
2Stability of the object's composition
If conventional microprocessors use global clocks to synchronize operations, then system coordination is achieved, but capacitive load increases and dynamic power consumption occurs continuously
Solution Approach 1:
The patent removes the global clock from the system architecture. Instead of using a centralized clock signal that continuously drives all circuits, the system operates with distributed or no clocking. This extraction eliminates the continuous capacitive loading on global clock wires and the associated dynamic power consumption, while system coordination is maintained through asynchronous handshaking protocols and local synchronization mechanisms.
Solution Approach 2:
The patent introduces asynchronous communication protocols and handshaking mechanisms as intermediaries to replace the global clock's coordination function. These intermediaries enable circuits to synchronize their operations without requiring a continuous clock signal, thereby maintaining system coordination while eliminating the continuous power consumption associated with global clock distribution.
3Adaptability or versatility
If conventional microprocessors re-operate to handle external interrupts, then interrupt processing is enabled, but unnecessary reactivation occurs and power consumption increases
Solution Approach 1:
The patent implements an event-driven architecture where the system automatically responds to external events without requiring full microprocessor reactivation. Event detection circuits monitor for specific conditions and trigger only the necessary processing routines, allowing the microprocessor to remain in a low-power state while maintaining the ability to handle interrupts efficiently. This self-service mechanism eliminates unnecessary reactivation and associated power consumption.
Solution Approach 2:
The patent employs event detection circuits that continuously monitor for external events in a low-power mode. When an event is detected, the system is already prepared to respond immediately without requiring full microprocessor reactivation. This preliminary event detection capability enables efficient interrupt handling while keeping the main processor in a low-power state, thereby reducing power consumption during interrupt processing.
Data Source
AI summary
Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.