Event Queue State Machine for SoC Power Task Offloading

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Solution Overview

Problem

System-on-chip (SoC) designs face complexity in managing multiple power islands and tasks, leading to system delays due to CPU overload, and existing solutions are not generic enough to be applicable across varying complexity platforms.

Innovation Solution

An integrated circuit with a memory, a mapping interface, and a state machine that stores functions, maps signals to functions, and re-maps them based on execution frequency, allowing for efficient power management and task execution across different power states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a CPU is used to manage tasks and power islands in SoC designs, then the system can handle multiple tasks and power domains, but the CPU becomes overloaded leading to system delays

Engineering Contradiction:
Improvecapability to manage multiple tasks and power islandsVSAvoidsystem delays due to CPU overload
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent introduces an event queue as an intermediary data structure between signal reception and function execution. The event queue stores event indices that represent pending tasks, allowing the system to buffer and manage multiple tasks without requiring the CPU to continuously poll or actively manage each task, thereby reducing CPU overload and system delays

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the task management burden from the CPU by implementing a dedicated state machine that autonomously processes events from the event queue. This state machine handles power island management and task execution independently, removing the overhead from the CPU and preventing system delays

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of operation

If individualised approaches are used to tailor process management to particular system requirements, then operation of that particular system is improved, but the approach is no longer applicable to other systems

Engineering Contradiction:
Improveoperation of particular systemVSAvoidapplicability to other systems
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal event queue and state machine architecture that can handle multiple types of events and functions through a common interface. The event queue stores generic event indices that can represent any task or power management operation, allowing the same hardware structure to be applied across different SoC complexities from IoT to multimedia platforms without system-specific customization

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If functions are executed in response to signals in a straightforward manner, then the system responds to events, but processing steps and power consumption increase

Engineering Contradiction:
Improveresponse to eventsVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary action by pre-storing event indices in the event queue that encode function identification information. When signals are received, the system simply retrieves and executes the pre-prepared event indices from the queue, avoiding the need for real-time signal analysis and function selection, thereby reducing processing steps and power consumption

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12072833B2Executing functions in response to reading event indices on an event queue by a state machine
Publication Date: 2024.08.27 IMAGINATION TECH LTD
  • US12072833B2 patent drawing
  • US12072833B2 patent drawing
  • US12072833B2 patent drawing

AI summary

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.