Event Message Receipt Mechanism With Atomic Counter Reset
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Solution Overview
Problem
Existing computer architectures face challenges in efficiently moving data between processors and memory, leading to performance and capacity constraints due to time and energy consumption, which limits advancements beyond transistor scaling.
Innovation Solution
Implementing compute-near-memory (CNM) systems with hybrid threading processors and custom compute fabrics that facilitate high-bandwidth, low-latency operations, using chiplet-based architectures and specialized processors to manage and coordinate threads, and employing a reliable event message mechanism to ensure accurate accounting of event messages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved between processors and memory using conventional shared memory and bus architectures, then system capacity can be maintained, but performance is constrained due to significant time and energy consumption
Solution Approach 1:
The patent divides the monolithic processor-memory system into distributed compute nodes, each with local memory and processing units. This segmentation allows compute operations to occur closer to data, reducing the time and energy required for data movement between centralized memory and processors.
Solution Approach 2:
The patent introduces a new architectural dimension by placing compute units directly within or near memory structures, creating a three-dimensional compute-near-memory architecture. This dimensional change eliminates the traditional sequential path between memory and processors, enabling parallel compute operations at multiple spatial levels.
2Productivity
If data is moved between processors and memory using conventional shared memory and bus architectures, then system capacity can be maintained, but energy consumption increases
Solution Approach 1:
The patent segments the system into distributed compute nodes with local memory, eliminating the need for energy-intensive data movement across centralized memory buses. Each node performs compute operations locally, dramatically reducing the energy required for data transmission.
Solution Approach 2:
Each compute node is self-sufficient with its own local memory and processing units, eliminating dependency on centralized memory resources. This self-service architecture reduces energy consumption by avoiding repeated data transfers over the system bus and enabling local compute operations.
3Reliability
If event message reception uses conventional polling or interrupt mechanisms, then system simplicity is maintained, but message accounting reliability deteriorates
Solution Approach 1:
The patent introduces an event message buffer as an intermediary structure between the message sender and receiver. This buffer acts as a reliable storage medium that ensures messages are accounted for, using atomic operations to maintain accurate message counts without requiring complex polling or interrupt handling.
Solution Approach 2:
The patent replaces mechanical polling and interrupt mechanisms with software-based atomic operations and memory barriers. This substitution eliminates the timing-critical nature of hardware interrupt systems while maintaining message accounting reliability through ordered memory operations.
4Speed
If compute operations are performed far from memory, then memory access patterns remain simple, but latency increases for compute-intensive operations
Solution Approach 1:
The patent creates a vertical integration of compute and memory by placing compute units within or adjacent to memory structures. This three-dimensional architecture reduces the physical distance and time required for memory access during compute operations, while maintaining simple horizontal memory access patterns.
Solution Approach 2:
The patent merges compute units and memory structures into integrated compute-near-memory blocks. This consolidation allows compute operations to access memory data with minimal latency, as the compute units are physically adjacent to or within the memory structure rather than separated by long data paths.
Data Source
AI summary
Devices and techniques for providing receipts for event messages in a processor are described herein. A system includes multiple memory-compute nodes coupled to one another over a scale fabric; a set of registers; and an event manager hardware circuitry to: receive an event message corresponding to an event, and the event associated with an event mode; track a counter value representing a number of received event messages related to the event, the counter value stored in the set of registers; compare the number of received event messages to a trigger value; and in response to the number of received event messages equaling the trigger value: use an atomic operation to reset the counter value in the set of registers while maintaining the event mode; and alert a thread of the event.