Event Registers for Parallel Processing Synchronization
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Solution Overview
Problem
Complex computer systems, such as neural network processors, face challenges in synchronizing and tracking the execution of multiple processing units due to their complex software and hardware configurations, leading to difficulties in managing parallel processing and identifying the root cause of stalls or errors.
Innovation Solution
The implementation of event registers and age bit registers allows for synchronization and tracking of execution across processing engines, using events to coordinate operations and generate notifications for debugging, enabling efficient management of parallel execution and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing units are used for parallel processing to improve performance, then productivity increases, but device complexity and difficulty of synchronization increase
Solution Approach 1:
The patent introduces event registers as intermediary components that mediate between multiple processing units. Each processing unit can set or clear event registers to signal completion of operations or readiness for next steps. This intermediary mechanism enables coordinated parallel processing without requiring complex direct inter-unit communication protocols, thus improving productivity while managing system complexity.
Solution Approach 2:
The patent implements feedback mechanisms where processing units monitor the state of event registers to determine when to proceed with next operations. This feedback loop allows processing units to automatically synchronize their execution based on completion signals from other units, enabling efficient parallel processing with minimal external coordination overhead.
2Productivity
If multiple processing units are used for parallel processing, then productivity increases, but execution tracking and error identification become more difficult
Solution Approach 1:
The patent uses event register states (set/cleared) as binary indicators to represent different execution phases and completion statuses. This state-based visualization method allows debugging tools to easily detect and track the execution state of multiple processing units by simply reading register values, transforming complex execution tracking into a simple state-detection problem.
Solution Approach 2:
Event registers serve as intermediary components that capture and store execution state information from multiple processing units. Debugging tools can query these registers to obtain a centralized view of system state, making it easy to identify which units are waiting, which have completed operations, and where execution bottlenecks or errors occur.
3Productivity
If complex circuits with multiple processing units are used, then productivity increases, but synchronization of execution becomes more challenging
Solution Approach 1:
The patent ensures continuous useful action by allowing processing units to proceed with independent operations as soon as their data dependencies are satisfied, rather than waiting for a global synchronization barrier. Event registers enable fine-grained synchronization where units only wait for specific events they depend on, maintaining continuous productive execution while ensuring proper coordination where needed.
Solution Approach 2:
The patent uses event registers to perform preliminary actions by setting or clearing events in advance of when other processing units need to proceed. This allows upstream units to signal readiness before downstream units are actually ready to receive the signal, enabling smooth handoff and reducing idle waiting time while maintaining synchronization reliability.
Data Source
AI summary
An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.