Event Slot Register Interface for CPU-Independent PMU Control
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Solution Overview
Problem
System-on-chip (SoC) designs face complexity in managing multiple power islands and tasks, leading to potential CPU overload and system delays, necessitating a more efficient and flexible power management solution that can operate independently of the CPU.
Innovation Solution
A lightweight power management unit (PMU) IC with a communications interface that includes an event slot with write and read registers, a state machine, and a memory system, allowing for programmable and flexible control of power domains, voltage switches, and clock management, enabling efficient power state transitions and event handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CPU is used to manage multiple power islands and tasks, then system management capability is improved, but CPU overload occurs leading to system delays
Solution Approach 1:
The patent divides the system into two distinct management layers: a lightweight PMU layer for real-time power island management and a higher-level CPU layer for complex task coordination. The PMU handles time-critical power management operations independently, segmenting the management functions to prevent CPU overload and system delays.
Solution Approach 2:
The PMU acts as an intermediary between the CPU and power islands, handling time-critical power management operations independently. This mediator approach allows the CPU to focus on high-level task coordination while the PMU manages real-time power state transitions, preventing CPU overload.
2Speed
If a lightweight PMU with event slot registers is used, then processing speed is improved, but device complexity increases
Solution Approach 1:
The PMU employs dynamic event slot registers that can be configured at runtime to handle different power management scenarios. The event queue and register architecture allow flexible, dynamic response to power management events, achieving high processing speed while maintaining manageable complexity through programmable configurations.
Solution Approach 2:
The patent utilizes configurable register parameters (event slot registers with write/read/compare capabilities) that can be programmed to handle different power management scenarios. By changing register parameters rather than hardware structure, the system achieves high processing speed for multiple scenarios without increasing physical device complexity.
Data Source
AI summary
A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.