Event Slot Register Addressing for CPU-Independent SoC Power Control
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Solution Overview
Problem
System-on-chip (SoC) designs face complexity in managing multiple power islands and tasks, leading to potential CPU overload and system delays, necessitating a more efficient and flexible power management solution that can operate independently of the CPU.
Innovation Solution
A lightweight power management unit (PMU) IC with a state machine and communications interface that allows for programmable and flexible power management, capable of responding to both hardware and software events, and controlling power domains, including voltage switches and clocks, to manage power states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CPU is used to manage tasks and power islands in SoC systems, then system management capabilities are provided, but the CPU becomes overloaded causing system delays
Solution Approach 1:
The patent divides the system management function into two separate components: a CPU for high-level task management and a dedicated state machine for power island management. This segmentation allows the CPU to focus on complex tasks while the state machine handles power management autonomously, preventing CPU overload and system delays.
Solution Approach 2:
The patent introduces a communications interface with event slots as an intermediary between the CPU and state machine. This interface includes write registers for the CPU to send commands and read registers for the state machine to report status, enabling efficient asynchronous communication without burdening the CPU.
2Productivity
If individualised approaches are used to tailor process management to specific system requirements, then operational efficiency for that system is improved, but the solution becomes inapplicable to other systems
Solution Approach 1:
The patent designs the state machine with a configurable event slot structure that can be programmed to handle different power management scenarios. The communications interface uses standardized register operations (write/read) that can be adapted to various SoC configurations, making the solution universally applicable while maintaining system-specific optimization through programming.
3Measurement precision
If multiple registers are provided in an event slot for detailed control, then management precision is improved, but address complexity increases
Solution Approach 1:
The patent merges multiple control functions into a single event slot address location. Each event slot contains multiple registers (write register for commands, read register for status, mask register for filtering, reference register for configuration), but all are accessed through one base address by the CPU, simplifying the address interface while maintaining precise control capabilities.
Data Source
AI summary
A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.